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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 141/169頁(yè) |
| 文件大小： | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
141
Figure 14 “J0” Synchronization Control
In the line side RX direction:
1. An 8kHz frame pulse is received by all devices at time t
2. Upon receipt of the 8kHz frame pulse, the SPECTRA-2488 outputs data (and J0) onto the
TelecomBus at time t
3. The TBS emits the serialized J0 8B/10B character approximately 35 clock cycles later at time t
1
4. The J0 character arrives at the input of the TSE A clock cycles later at time t
2
. A and B
represents the clock cycle delay of the links.
5. The TSE RJ0DLY value can be set to create a receive FIFO depth of approximately half the FIFO
length of 24 characters. The J0 character will be in the FIFO along with 11 more characters
approximately 23 clock cycles after the J0 character enters the TSE input. The cumulative time in
SYSCLK cycles from t
to t
plus the extra 23 clock cycle delay into the TSE receive FIFO is the the
time that should be used for the RJ0DLY value.
6. The TSE emits the J0 characters approximately 43 clock cycles after the J0 characters are read
out of the receive FIFOs (t
+ RJ0DLY) at time t
.
7. The J0 character is present at the MACH48 device B clock cycles later at time t
8. The S/UNI-MACH48 RJ0DLY value should be set using the same method as used to set the TSE
RJ0DLY value. (RJ0DLY = J0 character arrival time + 23 clock cycles to fill the receive FIFO
halfway.
In the line side TX direction:
1. An 8kHz frame pulse is received by all devices at time t
2. Approximately 7 + OJ0REF SYSCLK cycles after receiveing the the 8 kHz frame pulse on
OJ0REF, the S/UNI-MACH-48 outputs the J0 character to the TSE device . Since the arrival of J0
characters at the TSE receivers from the TBS and the S/UNI-MACH-48 must be aligned, the
OJ0REFDLY value at the S/UNI-MACH28 should be set to the cumulative latency of the TBS in
SYSCLK cycles (33-36) minus the 7 delay between OJ0REF and the J0 character output when
OJ0REFDLY=0.
3. The TSE outputs the J0 character at time t
c
4. The TBS receives the J0 character at time t
. Approximately 23 clock cycles following the arrival
of the J0 character, the TBS receive FIFO will be half full. The cumulative time from t
to t
in
SYSCLK cycles plus the additional 23 cycle delay into the TBS receive FIFOs should be used for
the TBS RJ0DLY value.
NOTE: In all cases J0 character arrival times specified are the nominal arrival times. This is
because the TX FIFO can impose a +/-4 cycle delay on the data. The nominal time assumes
the additional delay by the TX FIFO imposed is 0 cycles in all cases. The calculated RJ0DLY
values provided in the example will work in any case - the receive FIFOs may just be more or
less full than stated (12 characters full), depending on the state of the upstream TX FIFO.
23
SPECTRA-
2488
DJ0REF
AJ0J1
DJ0J1
TBS
RJ0FP
OJ0J1
IJ0J1
TSE
RJ0FP
S/UNI-MACH48
RJ0FP
OJ0REF
Parallel
TelecomBus
Serial LVDS
TelecomBus
t
1
Serial LVDS
TelecomBus
t
3
8 kHz reference frame pulse
distributed to all devices at t
0
t
o
t
2
t
4
t
a
t
b
t
c
t
d
t
e
t
o
35
t
1
t
2
A
t
3
t
4
B
t
b
t
c
B
t
a
A
t
d
t
e
23
RJ0DLY
TSE
23
RJ0DLY
MACH
RJ0DLY
TBS
28
OJ0REFDLY
MACH
46
RX
Direction
TX
Direction
43
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