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參數(shù)資料
| 型號： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 25/169頁 |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
25
6
Description
The PM5372 TSE is a monolithic CMOS integrated circuit that performs STS-1 granularity
cross-connecting.
The TSE receives data on 64 777.6 MHz LVDS links. Each link contains a STS-12/STM-4
stream. Bytes on the links are carried as 8B/10B characters. At minimum, each stream must
include a 8B/10B special framing character to allow the TSE to character and frame align the
stream. Additionally, the TSE can support a serial TelecomBus protocol, in which TelecomBus
control signals are encoded as 8B/10B special characters. Data is switched through the TSE in
8B/10B code words. The TSE performs character and frame alignment on each stream. The TSE
aligns data from multiple sources prior to switching the data. Data alignment is achieved by
synchronizing the Frame Aligners in transmitting their aligned frame data. The TSE switches the
STS-12 aligned data streams at STS-1 granularity through Time, Space, and then Time switch
stages. The time switch stages perform timeslot interchange on the STS-12 data stream. The
Space switch stage switches data from one STS-12 pipe to another. Each time slot is switched
independently in the Space switch stage.
The TSE supports software configurable dual-page switch settings. This permits new switch
settings to be stored in the inactive page of control settings, while the TSE operates on the active
page of control settings. The TSE switches between control setting pages on STS-1 frame
boundaries for hitless switchover through the device page select pin CMP. Block-by-block
switchover is facilitated by software configurable page select bits.
The TSE transmits data on 64 777.6 MHz LVDS links. As on the receive side, a link contains a
STS-12/STM-4 stream, encoded as 8B/10B characters. Prior to transmission and following
switching, the TSE must reprocess each stream for correct 8B/10B disparity.
The function of the TSE is explained with respect to the block diagram. The flow in the block
diagram is left-to-right. The left-most three units on each of the 64 STS-12 flows (LVDS
Receiver, Data Recovery Unit, and Receive 8B/10B Frame Aligner) receive, decode and align the
incoming flows. The Ingress Time Switch Elements perform timeslot interchange on the STS-12
stream. The Space Switch Element permits arbitrary permutations over space during each time
step. The Egress Time Switch Elements implements another STS-12 timeslot interchange. The
right-most three units (Transmit 8B/10B Disparity Encoder, Serializer, and LVDS Transmitter) re-
encode, serialize and transmit the output streams. Switch control is distributed among the time
and space switching modules. Switch control is organized into pages of control words which
determine what permutations are implemented for each of the twelve STS-1 positions (in time) at
each of the 64 ports (in space) for the switching stage. The Microprocessor Interface is used to
initialize the TSE and to access the switch control settings. JTAG is supported on non-LVDS
signal for board testing. The three modules (CSTR, CSU, and TXREF) provide clock and voltage
references for the other LVDS modules.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM5372BIP | 制造商:PMC-Sierra 功能描述: |
| PM5372-BI-P | 制造商:PMC-Sierra 功能描述: |
| PM5376HFI | 制造商:PMC-Sierra 功能描述: |
| PM5377 | 制造商:PMC 制造商全稱:PMC 功能描述:Single Chip 96-Port STS-1/STM-0 Cross-Connect |
| PM537CE | 制造商:ARTESYN 制造商全稱:Artesyn Technologies 功能描述:Single, dual and triple output 1 to 10.5 Watt AC/DC encapsulated modules |
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