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參數(shù)資料
| 型號： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 46/169頁 |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
46
Data is guaranteed to contain sufficient transition density to allow reliable operation of the data
recovery units by 8B/10B block coding and decoding provided by the T8DE and R8FA blocks.
At the system level, reliable operation will be obtained if proper signal integrity is maintained
through the signal path and the receiver requirements are respected. Specifically, a worst case
eye opening of 0.7UI and 100mV differential amplitude is needed. These conditions should be
achievable with a system architecture consisting of board traces, two sets of backplane connectors
and up to 1m of backplane interconnects. This assumes proper design of 100 differential lines
and minimization of discontinuities in the signal path. Due to power constraints, the output
differential amplitude is approximately 350mV.
The LVDS system is comprised of the LVDS Receiver (RXLV), LVDS Transmitter (TXLV),
Transmitter reference (TXREF), data recovery unit (DRU), parallel to serial converter (PISO),
and Clock Synthesis Unit (CSU).
9.1.1
LVDS Receiver (RXLV)
The RXLV block is a 777.6 Mb/s Low Voltage Differential Signaling (LVDS) Receiver according
to the IEEE 1596.3-1996 LVDS Specification.
The RXLV block is the receiver in Figure 7, accepting up to 777.6 Mb/s LVDS signals from the
transmitter, over RP[X]/RN[X] pins, amplifying them and converting them to digital signals, then
passing them to a data recovery unit (DRU). Holding to the IEEE 1596.3-1996 specification, the
RXLV has a differential input sensitivity better than 100mV, with no hysteresis. These are LVDS
receivers not CMOS. If a link is unused there is no electrical problem in leaving RP/RN floating
(as opposed to a CMOS input). Power dissipation is the same regardless of whether the input is
connected or not. No damage to the device will occur.
Unused links should be disabled in software. In this case the power for that link will be nearly
0mW. There is no requirement for how quickly this should be done. It simply results in lower
power dissipation since circuitry will be shut down. This is not mandatory for the device to
operate properly but is a good practice since it improves margins.
Hot-swapping is supported. The channel can be left enabled at all time and the device will sync
up once the far end transmitter is connected. There will be no effect on other channels.
There are 64 instances of the RXLV block on the TSE.
9.1.2
LVDS Transmitter (TXLV)
The TXLV block is a 777.6 Mbit/s Low Voltage Differential Signaling (LVDS) Transmitter
according to the IEEE 1596.3-1996 LVDS Specification.
The TXLV accepts 777.6 Mbit/s differential data from a “parallel-in, serial-out” (PISO) circuit
and then transmits the data off-chip as a low voltage differential signal on TP[X]/TN[X] pins.
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