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參數(shù)資料
| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 111/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
111
TSIN[3:0]
STS-1/STM-0 time slot #
0000
Invalid Time Slot
0001-1100
Time slot #1 to time slot #12
1101-1111
Invalid time slot
ECOVD[9:0]
The Character Overwrite data bits (ECOVD[9:0]) reports the data read after an indirect read
operation has completed. The data to be written to the control pages must be set up in this
register before triggering a write. ECOVD[9:0] reflects the last value read or written until the
completion of a subsequent indirect read operation. ECOVD[9:0] represents the data written
to the DINSEL port/ TSOUT timeslot of the ETSE block provided the ECHAR_OVWR[1:0]
bits are logic b’11. Otherwise, DINSEL and TINSEL control the output for the specified
port/timeslot.
Reserved[1:0]
The Reserved[1:0] bits must be set as shown for correct operation of the TSE.
ECHAR_OVWR[1:0]
The Character Overwrite Data Insertion Control bits (ECHAR_OVWR[1:0]) report the value
of the ECHAR_OVWR[1:0] bits read after an indirect read operation has completed. The
value of the ECHAR_OVWR[1:0] bits to be written to the control pages must be set up in
this register before triggering a write. ECHAR_OVWR[1:0] reflects the last value read or
written until the completion of a subsequent indirect read operation. The value of the
ECHAR_OVWR[1:0] bits control the source of the data bits that the muxing block outputs.
When set to logic b’00 the muxing block samples and reorders the holding buffers. When set
to logic b’11 then muxing block directly outputs the idle data (ECOVD[9:0]).
ECHAR_OVWR values of ‘b01 and ‘b10 are invalid.
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