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參數(shù)資料
| 型號： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 149/169頁 |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
149
13.2 Transmit Interface Timing
Figure 21 below shows the delay from assertion of RJ0FP to the transmit serial data links. Due to
the presence of FIFOs in the data path, the delay to the various links can differ by up to 8 cycles.
The minimum delay (RJ0DLY + 40 SYSCLK cycles) is shown to be incurred by one of the
transmit serial data links (TP[
X
]/TN[
X
]). The maximum delay (RJ0DLY + 47 cycles) is shown to
be incurred by another transmit serial data links (TP[
Y
]/TN[
Y
]). The suggested setting for
TJ0DLY results in a TJ0FP pulse at the time at which all the transmit serial links have transmitted
their respective J0 characters. The maximum delay from RJ0FP to the transmission of a J0 pulse
is RJ0DLY + 47 cycles. Therefore the suggested setting for TJ0DLY is RJ0DLY+ 47. The relative
phases of the links in Figure 21 are shown for illustrative purposes only. Links may have
different delays than what is shown.
Figure 21 Transmit Interface Timing
TP[
X
]/
TN[
X
]
TN[
Y
]/
TP[
Y
]
...
SYSCLK
RJ0FP
S4,3/
A2
S1,1/J0
S2,1/
Z0
S4,3/
A2
S1,1/J0
S2,1/
Z0
RJ0DLY+ Max Delay(47 cycles) to Last
J0
...
...
RJ0DLY + Min Delay(39
cycles) to First J0
...
...
...
...
TJ0FP
...
Figure 22 below shows the delay from CMP to the transmit serial data links. CMP is valid only at
the RJ0FP pulse time, whether RJ0FP is pulsed or not. It is ignored at other locations in the
transport frame. A change in value to the connection memory page signal (CMP) results in
changing the active switch settings. Given that CMP is sampled on the RJ0FP pulse time 0, the
first data that is switched according to the newly selected connection memory page are the A1
bytes of the second frame following the first J0 byte transmitted by the TSE after offset RJ0DLY
+ 40 cycles. In more absolute terms, the first A1s transmitted by the TSE between offset RJ0DLY
+ 40 + 19416 cycles and RJ0DLY + 47 + 19416 cycles, represent the first data switched
according the connection memory page selected by CMP at the RJ0FP pulse time 0.
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