參數(shù)資料
型號: PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 81/169頁
文件大?。?/td> 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
81
Register 0020H, 00024H, 0028H, 002CH: CSTR #1 – #4 Control
Bit
Type
Function
Default
Bit 15
R/W
Reserved[11]
0
Bit 14
R/W
Reserved[10]
0
Bit 13
R/W
Reserved[9]
0
Bit 12
R/W
Reserved[8]
0
Bit 11
R/W
Reserved[7]
0
Bit 10
R/W
Reserved[6]
1
Bit 9
R/W
Reserved[5]
0
Bit 8
R/W
Reserved[4]
0
Bit 7
R/W
Reserved[3]
0
Bit 6
R/W
Reserved[2]
0
Bit 5
R/W
Reserved[1]
0
Bit 4
R/W
CSU_ENB
0
Bit 3
R/W
CSU_RSTB
1
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
R/W
Reserved[0]
1
This register provides reset control and enable control for CSTR blocks #1 through #4
Reserved[11:0]
The Reserved[11:0] bits must be set to the indicated default value for correct operation of the
TSE.
CSU_RSTB
The CSU_RSTB signal is a software reset signal that forces the CSU into reset. The CSU is
reset when the CSU_RSTB is logic 0. The CSU is also reset by the TSE master analog reset
signal. When the CSU is reset, the reset signal should be held for at least 100us.
CSU_ENB
The CSU enable control signal (CSU_ENB) bit forces the CSU into low power configuration.
The CSU is disabled when CSU_ENB is logic 1. The CSU is enabled when CSU_ENB is
logic 0.
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