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參數(shù)資料
| 型號： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 127/169頁 |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
127
12.2 LVDS Optimizations
The LVDS interface implemented on the TBS and TSE follows the IEEE 1596.3-1996
specification with some minor exceptions. The changes are implemented to customize and
optimize the LVDS interface for the system and are described in detail below. Even with these
differences the LVDS interface should be compatible with the physical layer of other LVDS
interfaces. The differences from the IEEE specification include:
1. Faster rise/fall times (200 – 400) ps versus the specified (300 – 500) ps. Faster edge rates are
commonly used with higher speed LVDS interfaces in the industry to ease the interfacing.
The IEEE 1596.3-1996 edge rates are optimized for data rates below 400 Mbps Hysteresis is
not implemented in the receive LVDS interface.
2. Hysteresis is used in many implementations to negate the effect of noise that may exist on
unused LVDS links. Hysteresis was not implemented in the CHESS set devices to
minimize circuit complexity, power and cost. Instead, the RX interfaces and the DRUs for
unused links can be disabled (powered down) through register control in order to prevent
sensitivity to noise on these links
3. The LVDS transmitter contains an on-chip 100-ohm termination. Most implementations have
single 100-ohm termination on the receiver. By implementing a double termination (on both
the LVDS receiver and transmitter) a higher signal integrity and matching is ensured.
4. Although not a difference with the Layer 1 IEEE 1596.3-1996 specification, the Layer 2
8B/10B encoding is discussed here for completeness. 8B/10B encoding guarantees transition
density as compared to scrambled encoding, which provides only a certain probability of
transition density. This guaranteed transition density allows a simpler and more power-
effective data recovery unit, provides a more robust serial interface (greater trace or back-
plane distance achievable). It also negates the need for complete SONET framing since the
A1A2 and J0 bytes can be encoded into special escape characters of the LVDS data stream.
5. The device uses 20% resistors; not 10% as specified by the LVDS specification. They are
20% resistors since that was the highest tolerance resistor available for on-chip applications.
However, because they are integrated on-chip, this LVDS interface can achieve much better
signal integrity than one with off-chip terminations.
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