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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 148/169頁(yè) |
| 文件大小： | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
148
13 Functional Timing
13.1 Receive Interface Timing
Figure 20 below, shows the relative timing of the receive interface. The LVDS links carry
SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
justification events and alarm conditions are encoded in special control characters. The upstream
devices sourcing the links share a common clock and have a common transport frame alignment
that is synchronized by the Receive Serial Interface Frame Pulse signal (RJ0FP). Due to phase
noise of clock multiplication circuits and backplane routing discrepancies, the links will not phase
aligned to each other but are frequency locked. The delay from RJ0FP being sampled high to the
first and last J0 character is shown in Figure 20. In this example, the first J0 is delivered on link
RN[X]/RP[X]. The delay to the last J0 represents the time when the all the links have delivered
their J0 character. In the example below, link RN[Y]/RP[Y] is shown to be the slowest. The
minimum value for the internal programmable delay (RJ0DLY[13:0]) is the delay to the last J0
character plus 15. The maximum value is the delay to the first J0 character plus 30.
Consequently, the external system must ensure that the relative delays between all the receive
LVDS links be less than 16 bytes. The relative phases of the links in Figure 20 are shown for
illustrative purposes only. Links may have different delays relative to other links than what is
shown.
Figure 20 Receive Interface Timing
RP[
X
]/
RN[
X
]
RN[
Y
]/
RP[
Y
]
...
SYSCLK
RJ0FP
S4,3/
A2
S1,1/J0
S2,1/
Z0
S4,3/
A2
S1,1/J0
S2,1/
Z0
RJ0DLY[13:0] Delay
...
...
...
...
...
Max Delay between
First and Last J0s
Max Delay until internal Frame Pulse
...
...
...
Min Delay until internal
Frame Pulse
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