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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 140/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
140
The ingress FIFOs permit a variable latency in J0 arrival of up to 16 clock cycles. That is, the
largest tolerable delay between the slowest and fastest LVDS link of the 64 TSE LVDS links is 16
bytes. Consequently, the external system must ensure that the relative delays between all the 64
receive LVDS links be less than 16 bytes. The minimum value for the internal programmable
delay (RJ0DLY[13:0]) is the delay to the last (slowest) J0 character plus 15 bytes. The maximum
value is the delay to the first (fastest) J0 character plus 31 bytes. The actual programmed delay
should be based on the delay of the “slowest” of the 64 links – the link in which J0 arrives last
plus a small safety margin of 1 or 2 words. The magnitude of the clock cycle delay is bounded by
two parameters. First, the programmed delay register RJ0DLY is 14 bits. This implies that a
clock cycle delay of 214 –1 or 16,383 clock cycles can be programmed. However, the second
parameter, the frame rate (125 s), bounds the delay to one STS-12 frame or 9719 (9719 unique
values) clock cycles (125 s x 77.76 MHz), after which the next SONET frame begins. The TSE,
upon receiving the global frame pulse, will wait the programmed amount of time (56 clock cycles
+ cable length delays) before prompting each of the 64 links to emit their J0 character.
The number of clock cycles can be determined by simply adding the relevant device and cable
length latencies.
This synchronization mechanism is flexible enough to accommodate system paths with different
cumulative device latencies. Consider a TSE that is mated to a S/UNI-MACH48 on one link and
a SPECTRA-2488 feeding a TBS on the other link. The alternate data paths have different
delays; the SPECTRA-2488/TBS link has a greater delay than the S/UNI-MACH48 link delay.
In this case, the S/UNI-MACH48 is programmed to emit the J0 pulse later than SPECTRA-2488
(but aligned with the TBS serial output) such that the J0 from both sources arrive at the TSE
within the allowed 16-clock cycle window. The S/UNI-MACH48 programmed delay is 24 clock
cycles after the receipt of the frame pulse.
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