參數資料
型號: PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數: 45/169頁
文件大?。?/td> 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
45
9
Functional Description
9.1
LVDS Overview
The LVDS family of cells allow the implementation of 777.6 Mb/s LVDS links. A reference
clock of 77.76MHz is required. Four 777.6 Mb/s LVDS links form a high-speed serial
TelecomBus interface for passing an STS-48 aggregate data stream.
A generic LVDS link according to IEEE 1596.3-1996 is illustrated in Figure 7. The transmitter
drives a differential signal through a pair of 50 characteristic interconnects, such as board
traces, backplane traces, or short lengths of cable. The receiver presents a 100 differential
termination impedance to terminate the lines. Included in the standard is sufficient common-
mode range for the receiver to accommodate as much as 925mV of common-mode ground
difference.
Figure 7 Generic LVDS Link Block Diagram
Complete SERDES transceiver functionality is provided. Ten-bit parallel data is sampled by the
line rate divided-by-10 clock (77.76MHz SYSCLK) and then serialized at the line rate on the
LVDS output pins by a 777.6MHz clock synthesized from SYSCLK. Serial line rate LVDS data
is sampled and de-serialized to 10-bit parallel data. Parallel output transfers are synchronized to a
gated line rate divided-by-10 clock. The gating duty cycle is adjusted such that the throughput of
the parallel interface equals the receive input data rate. It is expected that the clock source of the
transmitter is the same as the clock source of the receiver to ensure the data throughput at both
ends of the link are identical.
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