參數(shù)資料
型號： PM5372-BI
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 5/169頁
文件大小： 989K
代理商： PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
5
Issue
No.
Issue
Date
Details of Change
Updated Reliability information (sec 23), and thermal information in sec 18.
Revised power sequencing information, added max junction temp, Theta JA
and Theta JC information, and chart of Theta JA vs. airflow
Added sections for LVDS hot swap information, power down calculations,
and trace length versus FIFO depth calculation .
Changed name of ETSE register bit in register 0NAAH to EACTIVE,
removed references to TCBMODE in sec 9.2 and in description of register
0NB0H
Revised sec 9.2 and 9.2.1 to further de-document TeleCombus mode.
Changed VIL(max) to 0.8V and VT+ to 2.2V based on characterization
report.
Revised Theta JA vs. Airflow table and Theta JC value with 560UBGA
information.
Updated operating power to 9.86W.
Changed operating temperature range to TC = -40°C to Tj=120C.
Revised section on J0 Synchronization.
Added instructions to check CSU lock status and to center transmit
FIFOs in Section 12.5. Added Section 12.8. Added diagnostic note
in TJ0FP pad description, amended TDI pad description to indicate
there is no pull up resistor on the pad, removed part of RES/RESK
pad description from datasheet, removed ATMSB, and DTMSB
register bits from datasheet, redocumented clear behavior of
indication register bits when WCIMODE=1, amended legal range of
values for RJ0DLY: 1 to 9719, added explanatory text to BUSY
register bits, removed RXLBSEL from datasheet, added functional
timing diagram for page switching using SPSEL, IPSEL, and EPSEL
register bits, corrected TJ0DLY description to indicate that the time
to TJ0FP is TJ0DLY+2, amended DLCV register bit description,
amended CENTER register bit description, to indicate that FIFO
depth is 3-4 deep following centering operation, removed RDC mode
from J0INS register bit description, corrected Boundary Scan
Register Table: previously reverse ordered, and OEB_D(I)
incorrectly identified as IO_CELL, updated System “J0” Timing
diagram, added input pad tolerance, output pad overshoot, latchup
current for RESK in Absolute Maximum Ratings table, added typical
and max operating currents to D.C Characteristics table, corrected
mechanical information table with respect to package thickness.
Finalized pin out, register setting and functions
4
October
2000
3
April
2000
January
2000
2
Register Description modification, package and pinout information,
added functional timing descriptions and scan test registers,
changed tolerances of 1.8V supply to +-5%.
Document created
1
June 1999
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