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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 93/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
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12/15/98 5:14 PM 24377002.doc
protection. It must connect the appropriate pins of all
Pentium II Xeon processor system bus agents.
A correct parity signal is high if an even number of
covered signals are low and low if an odd number of
covered signals are low. While RS[2:0]# = 000,
RSP# is also high, since this indicates it is not being
driven by any agent guaranteeing correct parity.
9.1.42.
SA[2:0] (I)
The SA (Select Address) pins are decoded on the
SMBus in conjunction with the upper address bits in
order to maintain unique addresses on the SMBus in
a system with multiple Pentium II Xeon processors.
To set an SA line high, a pull-up resistor should be
used that is no larger than 1K
. To set an SA line as
low, SA1 and SA0 can be left unconnected. To set
SA2 as low, it should be pulled to ground (~10k
).
SA2 can also be tri-stated to define additional
addresses for the thermal sensor. A tri-state or “Z”
state on this pin is achieved by leaving this pin
unconnected.
Of the addresses broadcast across the SMBus, the
memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to
enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to
V
SS
(‘0’) for the Scratch EEPROM and pulled to
V
CCSMBus
(‘1’) for the Processor Information ROM.
The “XX” bits are defined by the processor slot via
the SA0 and SA1 pins on the SC330 connector.
These address pins are pulled down weakly (10k
)
on the cartridge to ensure that the memory
components are in a known state in systems which
do not support the SMBus, or only support a partial
implementation. The “Z” bit is the read/write bit for the
serial bus transaction.
The thermal sensor internally decodes 1 of 3 upper
address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The
device’s addressing, as implemented, includes a Hi-Z
state for one address pin (SA2), and therefore
supports 6 unique resulting addresses. The ability of
the system to drive this pin to a Hi-Z state is
dependent on the motherboard implementation (The
pin must be left floating). The system should drive
SA1 and SA0, and will be pulled low (if not driven) by
the 10k
pull-down resistor on the processor
substrate. Driving these signals to a Hi-Z state would
cause ambiguity in the memory device address
decode, possibly resulting in the devices not
responding, thus timing out or hanging the SMBus.
As before, the “Z” bit is the read/write bit for the serial
bus transaction.
For more information on the usage of these pins, see
Section 4.3.7.
9.1.43.
SMBALERT# (O)
SMBALERT# is an asynchronous interrupt line
associated with the SMBus Thermal Sensor device.
9.1.44.
SMBCLK (I)
The SMBCLK (SMBus Clock) signal is an input clock
to the system management logic which is required for
operation of the system management features of the
Pentium
II
Xeon
processor.
asynchronous to other clocks to the processor.
This
clock
is
9.1.45.
SMBDAT (I/O)
The SMBDAT (SMBus DATa) signal is the data
signal for the SMBus. This signal provides the single-
bit mechanism for transferring data between SMBus
devices.
9.1.46.
SELFSB0 (I/O)
Current Pentium II Xeon processors do not have a
selectable system bus speed option. SELFSB0
should be left as an open on the motherboard to
ensure compatibility with future processors.
9.1.47.
SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop
Grant state, causes processors to enter the Sleep
state. During Sleep state, the processor stops
providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or
interrupts. The processor will recognize only
assertions of the SLP#, STPCLK#, and RESET#
signals while in Sleep state. If SLP# is deasserted,
the processor exits Sleep state and returns to Stop
Grant state, restarting its internal clock signals to the
bus and APIC processor core units.
9.1.48.
SMI# (I)
The SMI# (System Management Interrupt) signal is
asserted asynchronously by system logic. On
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