- 您現在的位置：買賣IC網 > PDF目錄369993 > pentium II xeon processor (Intel Corp.) pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) PDF資料下載
參數資料
| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數： | 86/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁當前第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
86
12/15/98 5:14 PM 24377002.doc
APPENDIX A
9.0.
APPENDIX
This appendix provides an alphabetical listing of all
Pentium II Xeon processor signals and tables that
summarize the signals by direction: output, input, and
I/O.
9.1.
Alphabetical Signals Reference
This section provides an alphabetical listing of all
Pentium II Xeon processor signals.
9.1.1.
A[35:03]# (I/O)
The A[35:3]# (Address) signals define a 2
36
-byte
physical memory address space. When ADS# is
active, these pins transmit the address of a
transaction; when ADS# is inactive, these pins
transmit transaction type information. These signals
must connect the appropriate pins of all agents on
the Pentium II Xeon processor system bus. The
A[35:24]# signals are parity-protected by the AP1#
parity signal, and the A[23:03]# signals are parity-
protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the
processors sample the A[35:03]# pins to determine
their power-on configuration. See the Pentium
II
Processor Developer’s Manualfor details.
9.1.2.
A20M# (I)
If the A20M# (Address-20 Mask) input signal is
asserted, the Pentium II Xeon processor masks
physical address bit 20 (A20#) before looking up a
line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor’s address wrap-around
at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
During active RESET#, each processor begins
sampling the A20M#, IGNNE#, and LINT[1:0] values
to determine the ratio of core-clock frequency to bus-
clock frequency. See Table 1. On the active-to-
inactive transition of RESET#, each processor
latches these signals and freezes the frequency ratio
internally. System logic must then release these
signals for normal operation.
9.1.3.
ADS# (I/O)
The ADS# (Address Strobe) signal is asserted to
indicate the validity of the transaction address on the
A[35:03]# pins. All bus agents observe the ADS#
activation to begin parity
checking, address decode, internal snoop, or
deferred reply ID match operations associated with
the new transaction. This signal must connect the
appropriate pins on all Pentium II Xeon processor
system bus agents.
checking,
protocol
9.1.4.
AERR# (I/O)
The AERR# (Address Parity Error) signal is
observed and driven by all Pentium II Xeon
processor system bus agents, and if used, must
connect the appropriate pins on all Pentium II Xeon
processor system bus agents. AERR# observation is
optionally enabled during power-on configuration; if
enabled, a valid assertion of AERR# aborts the
current transaction.
If AERR# observation is disabled during power-on
configuration, a central agent may handle an
assertion of AERR# as appropriate to the Machine
Check Architecture (MCA) of the system.
9.1.5.
AP[1:0]# (I/O)
The AP[1:0]# (Address Parity) signals are driven by
the request initiator along with ADS#, A[35:03]#,
REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and
AP0# covers A[23:03]#. A correct parity signal is high
if an even number of covered signals are low and low
if an odd number of covered signals are low. This
allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate
相關PDF資料 |
PDF描述 |
|---|---|
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術奔騰超速轉動處理器) |
| pentium pro processor | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復。