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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 41/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
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12/15/98 5:14 PM 24377002.doc
bus while in Stop-Grant state or in Auto HALT Power
Down state. When a snoop transaction is presented
upon the system bus, the processor will enter the
HALT/Grant Snoop state. The processor will stay in
this state until the snoop on the system bus has been
serviced (whether by the processor or another agent
on the system bus). After the snoop is serviced, the
processor will return to the Stop-Grant state or Auto
HALT Power Down state, as appropriate.
4.2.5.
SLEEP STATE—STATE 5
The Sleep state is a very low power state in which
the processor maintains its context, maintains the
PLL, and has stopped all internal clocks. The Sleep
state can only be entered from Stop-Grant state.
Once in the Stop-Grant state (verified by the
termination of the Stop-Grant Bus transaction cycle),
the SLP# pin can be asserted, causing the Pentium II
Xeon processor to enter the Sleep state. The system
must wait 100 BCLK cycles after the completion of
the Stop-Grant Bus cycle before SLP# is asserted.
For an MP system, all processors must complete the
Stop Grant bus cycle before the subsequent 100
BCLK wait and assertion of SLP# can occur. The
processor is in Sleep state 10 BCLKs after the
assertion of the SLP# pin. The latency to exit the
Sleep state is 10 BCLK cycles. The SLP# pin is not
recognized in the Normal, or Auto HALT States.
Snoop events that occur during a transition into or
out of Sleep state will cause unpredictable behavior.
Therefore, transactions should be blocked by system
logic during these transitions.
In the Sleep state, the processor is incapable of
responding to snoop transactions or latching interrupt
signals immediately after the assertion of the SLP#
pin (one exception is RESET# which causes the
processor to re-initialize itself). The system core logic
must detect these events and deassert the SLP#
signal (and subsequently deassert the STPCLK#
signal for interrupts) for the processor to correctly
interpret any bus transaction or signal transition.
Once in the Sleep state, the SLP# pin can be
deasserted if another asynchronous event occurs.
No transitions or assertions of signals are allowed on
the system bus while the Pentium II Xeon processor
is in Sleep state. Any transition on an input signal
(with the exception of SLP# or RESET#) before the
processor has returned to Stop Grant state will result
in unpredictable behavior.
If RESET# is driven active while the processor is in
the Sleep state, and held active as specified in the
RESET# pin specification, then the processor will
reset itself, ignoring the transition through Stop Grant
State. If RESET# is driven active while the processor
is in the Sleep State and normal operation is desired,
the SLP# and STPCLK# should be deasserted
immediately after RESET# is asserted.
4.2.6.
CLOCK CONTROL
The Pentium II Xeon processor provides the clock
signal to the L2 Cache. The processor does not stop
this clock to the second level cache during Auto
HALT Power Down or Stop-Grant states. During
Auto HALT Power Down and Stop-Grant states, the
processor will continue to process the snoop phase
of a system bus cycle. The PICCLK signal should not
be removed during the Auto HALT Power Down or
Stop-Grant states.
When the processor is in the Sleep state, it will not
respond to interrupts or snoop transactions. PICCLK
can be removed during the Sleep state.
The processor will not enter any low power states
until all internal queues for the second level cache
are empty. When re-entering Normal state, the
processor will resume processing external cache
requests as soon as new requests are encountered.
4.3.
System Management Bus
(SMBus) Interface
The Pentium II Xeon processor includes an SMBus
interface which allows access to several processor
features,
including
two
(referred to as the Processor Information ROM and
the Scratch EEPROM) and a thermal sensor on the
Pentium II Xeon processor substrate. These devices
and their features are described below.
memory
components
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