PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/16/98 1:24 PM 24377003.doc
5.1.2. PLATE FLATNESS
SPECIFICATION..................................54
5.2. Processor Thermal Analysis........................54
5.2.1. THERMAL SOLUTION
PERFORMANCE .................................54
5.2.2. THERMAL PLATE TO COOLING
SOLUTION INTERFACE
MANAGEMENT GUIDE.......................55
5.2.3. MEASUREMENTS FOR THERMAL
SPECIFICATIONS ...............................57
5.2.3.1. Thermal Plate Temperature
Measurement.................................57
5.2.3.2. Cover Temperature Measurement
Guideline........................................58
6.0. MECHANICAL SPECIFICATIONS.................58
6.1. Weight..........................................................63
6.2. Cartridge to Connector Mating Details.........63
6.3. Pentium II Xeon Processor Substrate
Edge Finger Signal Listing...........................65
7.0. BOXED PROCESSOR SPECIFICATIONS....74
7.1.Introduction...................................................74
7.2.Mechanical Specifications............................74
7.2.1. BOXED PROCESSOR HEATSINK
DIMENSIONS.......................................77
7.2.2. BOXED PROCESSOR HEATSINK
WEIGHT ...............................................78
7.2.3. BOXED PROCESSOR RETENTION
MECHANISM........................................78
7.3.Thermal Specifications.................................78
7.3.1. BOXED PROCESSOR COOLING
REQUIREMENTS ................................78
7.3.2. THERMAL EVALUATION ....................78
8.0. INTEGRATION TOOLS..................................78
8.1.In-Target Probe (ITP) for Pentium II
Xeon Processors......................................78
8.1.1. PRIMARY FUNCTION .........................79
8.1.2. DEBUG PORT CONNECTOR
DESCRIPTION.....................................79
8.1.3. DEBUG PORT SIGNAL
DESCRIPTIONS ..................................79
8.1.4. DEBUG PORT SIGNAL NOTES..........82
8.1.4.1. General Signal Quality Notes ........83
8.1.4.2. Signal Note: DBRESET#...............83
8.1.4.3. Signal Note: TDO and TDI.............83
8.1.4.4. Signal Note: TCK...........................83
8.1.5. USING BOUNDARY SCAN TO
COMMUNICATE TO THE
PROCESSOR.......................................85
8.2.Integration Tool (Logic Analyzer)
Considerations.............................................85
8.2.1. INTEGRATION TOOL MECHANICAL
KEEPOUTS..........................................85
9.0. APPENDIX ......................................................86
9.1.Alphabetical Signals Reference....................86
9.1.1. A[35:03]# (I/O) ......................................86
9.1.2. A20M# (I)..............................................86
9.1.3. ADS# (I/O)............................................86
9.1.4. AERR# (I/O)..........................................86
9.1.5. AP[1:0]# (I/O)........................................86
9.1.6. BCLK (I)................................................87
9.1.7. BERR# (I/O)..........................................87
9.1.8. BINIT# (I/O) ..........................................87
9.1.9. BNR# (I/O)............................................87
9.1.10.
BP[3:2]# (I/O) ...................................87
9.1.11.
BPM[1:0]# (I/O) ................................87
9.1.12.
BPRI# (I)...........................................87
9.1.13.
BR0# (I/O), BR[3:1]# (I)....................87
9.1.14.
D[63:00]# (I/O)..................................89
9.1.15.
DBSY# (I/O).....................................89
9.1.16.
DEFER# (I).......................................89
9.1.17.
DEP[7:0]# (I/O).................................89
9.1.18.
DRDY# (I/O).....................................89
9.1.19.
EMI...................................................89
9.1.20.
FERR# (O).......................................89
9.1.21.
FLUSH# (I).......................................89
9.1.22.
FRCERR (I/O)..................................89
9.1.23.
HIT# (I/O), HITM# (I/O)....................90
9.1.24.
IERR# (O) ........................................90
9.1.25.
IGNNE# (I) .......................................90
9.1.26.
INIT# (I)............................................90
9.1.27.
INTR - SEE LINT[0]..........................90
9.1.28.
LINT[1:0] (I)......................................90
9.1.29.
LOCK# (I/O).....................................91
9.1.30.
NMI - SEE LINT[1] ...........................91
9.1.31.
PICCLK (I)........................................91
9.1.32.
PICD[1:0] (I/O) .................................91