參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 20/97頁(yè)
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
20
12/15/98 5:14 PM 24377002.doc
Flexible Mother Board (FMB) capable of
accepting all types of Pentium II Xeon
processors.
Specifications
specifications for case temperature, clock frequency
and input voltages.
Care should be taken to read
all notes associated with each parameter.
are
only
valid
while
meeting
Table 5. Voltage Specifications
1
Symbol
Parameter
Min
Typ
Max
Unit
Notes
V
CCCORE
V
CC
for processor core
FMB
1
All products
1.8-2.1
2.00
V
2, 3, 4
V
CCCORE
Tolerance,
Static
Processor core voltage static
tolerance at edge fingers
-0.085
0.085
V
7
V
CCCORE
Tolerance,
Transient
Processor core voltage transient
tolerance at edge fingers
-0.130
0.130
V
7
V
CCL2
V
CC
for second level cache
FMB
1
400 MHz
450 MHz
1.8-2.8
2.5 2.7
V
3, 5
V
CCL2
Tolerance,
Static
Static tolerance at edge fingers of
second level cache supply
-0.085
0.085
V
7
V
CCL2
Tolerance,
Transient
Transient tolerance at edge
fingers of second level cache
supply
-0.125
0.125
V
7
V
TT
AGTL+ bus termination voltage
1.365
1.50
1.635
V
6
V
CCSMBus
SMBus supply voltage
3.135
3.3
3.465
V
3.3 V±5%
V
CCTAP
TAP supply voltage
2.375
2.50
2.625
V
2.5 V±5%
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. “FMB” is a
suggested design guideline for flexible motherboard design.
V
CCCORE
supplies the processor core. FMB refers to the range of possible set points to expect for future Pentium
II
Xeon processors.
These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is
required. See Section 2.5. for more information.
Use the Typical Voltage specification along with the Tolerance specifications to provide correct voltage regulation to the
processor.
V
supplies the L2 cache. Unless otherwise noted, this specification applies to all Pentium II Xeon processor
frequencies and cache sizes. This parameter is measured at the processor edge fingers.
V
TT
must be held to 1.5 V ±9%. It is recommended that V
TT
be held to 1.5 V ±3% while the Pentium II Xeon processor
system bus is idle. This parameter is measured at the processor edge fingers. The SC330 connector is specified to have a
pin self-inductance of 6.0 nH maximum, a pin-to-pin capacitance of 2 pF (maximum at 1 MHz), and an average contact
resistance over the 6 V
TT
pins of 15m
maximum.
These are the tolerance requirements, across a 20 MHz bandwidth,
at the processor edge fingers.
The requirements at
the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to
the processor core. Voltage must return to within the static voltage specification within 100 us after the transient event.
The SC330 connector is specified to have a pin self-inductance of 6.0 nH maximum, a pin-to-pin capacitance of 2 pF
(maximum at 1 MHz), and an average contact resistance of 15m
maximum in order to function with the Intel specified
voltage regulator module (VRM 8.2 or VRM 8.3). Contact Intel for testing details of these parameters. Not 100% tested.
Specified by design characterization.
2.
3.
4.
5.
6.
7.
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