參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 16/97頁(yè)
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
16
12/15/98 5:14 PM 24377002.doc
Note that the ‘11111’ (all opens) ID can be used to
detect the absence of a processor core in a given
slot as long as the power supply used does not affect
these lines. Detection logic and pull-ups should not
affect VID inputs at the power source. (See Section
9.0.)
The VID pins should be pulled up to a TTL-
compatible level with external resistors to the power
source of the regulator only if required by the
regulator or external logic monitoring the VID[4:0]
signals. The power source chosen must be
guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the
possibility of the processor supply going above
V
CCCORE
in the event of a failure in the supply for the
VID lines. In the case of a DC-to-DC converter, this
can be accomplished by using the input voltage to
the converter for the VID line pull-ups. A resistor of
greater than or equal to 10k
may be used to
connect the VID signals to the converter input. See
the VRM 8.2 DC–DC Converter Design Guidelines
and/or
VRM
8.3
DC–DC
Guidelines for further information.
Converter
Design
2.6.
System Bus Unused Pins and
Test Pins
All RESERVED_XXX pins must remain unconnected.
Connection of RESERVED_XXX pins to V
CCCORE
,
V
CCL2
, V
SS
, V
TT
, to each other, or to any other signal
can result in component malfunction or incompatibility
with future members of the Pentium II Xeon processor
family. See Section 6.0. for a pin listing of the processor
edge connector for the location of each reserved pin.
The TEST_25_A62 pin must be connected to 2.5 V
via a pull-up resistor of between 1k
and 10k
.
TEST_VCC_CORE
must
individually
to
V
CCCORE
(approximately) resistor. TEST_VTT pins must each
be connected individually to V
TT
with a ~150
resistor. TEST_VSS pins must each be connected
individually to V
SS
with a ~1k
resistor.
each
through
be
connected
a
~10k
PICCLK must always be driven with a valid clock
input. and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A
separate pull-up resistor to 2.5 V (keep trace short) is
required for each PICD line.
For reliable operation, always connect unused inputs
to an appropriate signal level. Unused AGTL+ inputs
should be left as no connects; AGTL+ termination on
the processor provides a high level. Unused active
low CMOS inputs should be connected to 2.5 V with
a ~10k
resistor. Unused active high CMOS inputs
should be connected to ground (V
SS
). Unused
outputs may be left unconnected. A resistor must be
used when tying bi-directional signals to power or
ground. When tying any signal to power or ground, a
resistor will also allow for system testability. For
correct operation when using a logic analyzer
interface,
refer
to
Section 8.0.
considerations.
for
design
2.7.
System Bus Signal Groups
In order to simplify the following discussion, the
system bus signals have been combined into groups
by buffer type. All system bus outputs should be
treated as open drainand require a hi-level source
provided externally by the termination or pull-up
resistor.
AGTL+ input signals have differential input buffers,
which use 2/3 V
TT
as a reference level. AGTL+
output signals require termination to 1.5 V. In this
document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly, “AGTL+ Output” refers to
the AGTL+ output group as well as the AGTL+ I/O
group when driving. The AGTL+ buffers employ
active negation for one clock cycle after assertion to
improve rise times.
The CMOS, Clock, APIC, and TAP inputs can each
be driven from ground to 2.5 V. The CMOS, APIC,
and TAP outputs are open drain and should be pulled
high to 2.5 V. This ensures not only correct operation
for current Pentium II Xeon processors, but
compatibility for future Pentium II Xeon processor
products as well. There is no active negation on
CMOS outputs. ~150
resistors are expected on the
PICD[1:0] lines. Timings are specified into the load
resistance as defined in the AC timing tables. See
Section 8.0. for design considerations for debug
equipment.
The SMBus signals should be driven using standard
3.3 V CMOS logic levels.
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