PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
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1.0.
INTRODUCTION
The Pentium II Xeon processor is a follow-on to the
Pentium Pro and Pentium II processors. The
Pentium II Xeon processor, like the Pentium Pro
and Pentium II processors, implements a Dynamic
Execution micro-architecture—a unique combination of
multiple branch prediction, data flow analysis, and
speculative execution. This enables Pentium II
Xeon processors to deliver higher performance than
the Pentium processor, while maintaining binary
compatibility with all previous Intel Architecture
processors. The Pentium II Xeon processor is
available in 512K, 1M and 2 MB L2 cache options.
The Pentium II Xeon processor improves upon the
Pentium
Pro
processor
technology for 3-D compute-intensive applications,
and by utilizing the S.E.C. (Single Edge Contact)
package technology first introduced on the Pentium
II processor. This new packaging technology allows
Pentium II Xeon processors to implement the Dual
Independent Bus Architecture and have up to 2-
MBytes of level 2 cache. Like the Pentium Pro
processor, level 2 cache communication occurs at
the full speed of the processor core.
by
adding
MMX
A significant feature of the Pentium II Xeon
processor, from a system perspective, is the built-in
direct multiprocessing support. For systems with up
to four processors, it is important to consider the
additional power burdens and signal integrity issues
of supporting multiple loads on a high speed bus.
The Pentium II Xeon processor supports both
uniprocessor and multiprocessor implementations
with up to four processor on each local processor
bus, or system bus.
The Pentium II Xeon processor system bus
operates using GTL+ signaling levels with a new
type of buffer utilizing active negation and multiple
terminations. This new bus logic is called Assisted
Gunning Transistor Logic, or AGTL+. The Pentium
II Xeon processors also deviate from the Pentium
Pro processor in implementing an S.E.C. cartridge
package supported by the SC330 connector. (See
Section
6.0.
for
the
specifications.) This document provides information
to allow the user to design a system using Pentium
II Xeon processors.
processor
mechanical
1.1.
Terminology
In this document, a ‘#’ symbol after a signal name
refers to an active low signal. This means that a
signal is in the active state (based on the name of
the signal) when driven to a low level. For example,
when FLUSH# is low, a flush has been requested.
When NMI is high, a nonmaskable interrupt has
occurred. In the case of lines where the name does
not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’
symbol implies that the signal is inverted. For
example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D
[3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H= High
logic level, L= Low logic level).
The term ‘system bus’ refers to the interface
between the processor, system core logic and other
bus agents. The system bus is a multiprocessing
interface to processors, memory and I/O. The term
‘cache bus’ refers to the interface between the
processor and the L2 cache. The cache bus does
NOT connect to the system bus, and is not
accessible by other agents on the system bus.
Cache coherency is maintained with other agents
on the system bus through the MESI cache protocol
as supported by the HIT# and HITM# bus signals.
The term “Pentium II Xeon processor” refers to the
cartridge package which interfaces to a host system
board through a SC330 connector. Pentium II Xeon
processors include a processor core, a level 2
cache, system bus termination and various system
management features. The Pentium II Xeon
processor includes a thermal plate for cooling
solution attachment and a protective cover.
1.1.1.
S.E.C. Cartridge Terminology
The following terms are used often in this document
and are explained here for clarification:
Cover
—The processor casing on the opposite
side of the thermal plate.
Pentium
II Xeon processor
—The 100 MHz
SC330 product including internal components,
substrate, thermal plate and cover.