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| 型號(hào)： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 18/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
18
12/15/98 5:14 PM 24377002.doc
2.7.1.
ASYNCHRONOUS VS.
SYNCHRONOUS FOR SYSTEM BUS
SIGNALS
All AGTL+ signals are synchronous to BCLK. All of
the CMOS, Clock, APIC, and TAP signals can be
applied asynchronously to BCLK, except when
running
two
processors
Synchronization logic is required on signals going to
both processors in order to run in FRC mode. The
TAP logic can not be used while a processor is
running in an FRC pair, and the TAP signals should
therefore be at the appropriate inactive levels for
FRC operation.
as
an
FRC
pair.
Also note the timing requirements for FRC mode
operation. With FRC enabled, PICCLK must be 1/4
the frequency of BCLK, synchronized with respect to
BCLK, and must always lag BCLK as specified in
Table 15 and Figure 8.
All APIC signals are synchronous to PICCLK. All
TAP signals are synchronous to TCK. All SMBus
signals are synchronous to SMBCLK. TCK and
SMBCLK may always be asynchronous to all other
clocks.
2.8.
Test Access Port (TAP)
Connection
Depending on the voltage levels supported by other
components in the Test Access Port (TAP) logic, it is
recommended that the Pentium II Xeon processors
be first in the TAP chain and followed by any other
components within the system. A voltage translation
buffer should be used to drive the next device in the
chain unless a 3.3 V or 5 V component is used that is
capable of accepting a 2.5 V input. Similar
considerations must be made for TCK, TMS, and
TRST#. Multiple copies of each TAP signal may be
required if multiple voltage levels are needed within a
system.
NOTE
TDI is pulled up to Vcc
with ~150
on the
Pentium II Xeon processor cartridge. An open
drain signal driving this pin must be able to
deliver sufficient current to drive the signal
low. Also, no resistor should exist in the
system design on this pin as it would be in
parallel with this resistor.
A Debug Port is described in Section 8.0. The Debug
Port must be placed at the start and end of the TAP
chain with TDI to the first component coming from the
Debug Port and TDO from the last component going
to the Debug Port. In an MP system, be cautious
when including an empty SC330 connector in the
scan chain. All connectors in the scan chain must
have a processor or termination card installed to
complete the chain between TDI and TDO or the
system must support a method to bypass the empty
connectors; SC330 terminator substrates should tie
TDI directly to TDO. (See Section 5.0. for more
details.)
2.9.
Maximum Ratings
Table 4 contains Pentium II Xeon processor stress
ratings. Functional operation at the absolute
maximum and minimum is not implied nor
guaranteed. The processor should not receive a
clock while subjected to these conditions. Functional
operating conditions are given in the AC and DC
tables. Extended exposure to the maximum ratings
may affect device reliability. Furthermore, although
the processor contains protective circuitry to resist
damage from static electric discharge, one should
always take precautions to avoid high static voltages
or electric fields.
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