參數(shù)資料
型號： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁數(shù)： 5/97頁
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
5
12/15/98 5:14 PM 24377002.doc
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9.2.Signal Summaries ........................................95
PRDY# (O).......................................91
PREQ# (I).........................................91
PWREN[1:0] (I) ................................91
PWRGOOD (I).................................91
REQ[4:0]# (I/O)................................92
RESET# (I).......................................92
RP# (I/O)..........................................92
RS[2:0]# (I).......................................92
RSP# (I) ...........................................92
SA[2:0] (I).........................................93
SMBALERT# (O) .............................93
SMBCLK (I)......................................93
SMBDAT (I/O)..................................93
SELFSB0 (I/O).................................93
SLP# (I)............................................93
SMI# (I).............................................93
STPCLK# (I).....................................94
TCK (I)..............................................94
TDI (I)...............................................94
TDO (O) ...........................................94
TEST_25_A62 (I).............................94
TEST_VCC_CORE_XXX (I)............94
THERMTRIP# (O)............................94
TMS (I) .............................................94
TRDY# (I).........................................94
TRST# (I) .........................................94
VID_L2[4:0], VID_CORE[4:0](O).....94
WP (I)...............................................95
FIGURES
Figure 1. Timing Diagram of Clock Ratio
Signals................................................13
Figure 2. Logical Schematic for Clock Ratio Pin
Sharing................................................13
Figure 3. I-V Curve for nMOS Device.................22
Figure 4. BCLK, PICCLK, TCK Generic Clock
Waveform ...........................................29
Figure 5. SMBCLK Clock Waveform ..................30
Figure 6. Valid Delay Timings.............................30
Figure 7. Setup and Hold Timings.......................31
Figure 8. FRC Mode BCLK to PICCLK Timing...31
Figure 9. System Bus Reset and Configuration
Timings ...............................................32
Figure 10. Power-On Reset and Configuration
Timings ...............................................32
Figure 11. Test Timings (Boundary Scan)..........33
Figure 12. Test Reset Timings............................33
Figure 13. BCLK, TCK, PICCLK Generic Clock
Waveform at the Processor Core
Pins.....................................................34
Figure 14. Low to High AGTL+ Receiver
Ringback Tolerance............................36
Figure 15. Non-AGTL+ Overshoot/Undershoot,
Settling Limit, and Ringback ...............37
Figure 16. Stop Clock State Machine..................40
Figure 17. Logical Schematic of SMBus
Circuitry...............................................42
Figure 18. Thermal Plate View............................52
Figure 19. Plate Flatness Reference...................54
Figure 20. Interface Agent Dispensing Areas
and Thermal Plate Temperature
Measurement Points...........................56
Figure 21. Technique for Measuring TPLATE
with 0° Angle Attachment....................57
Figure 22. Technique for Measuring TPLATE
with 90° Angle Attachment..................57
Figure 23. Guideline Locations for Cover
Temperature (TCOVER)
Thermocouple Placement...................58
Figure 24. Isometric View of Pentium II Xeon
Processor S.E.C. Cartridge................59
Figure 25. S.E.C. Cartridge Cooling Solution
Attach Details......................................60
Figure 26. S.E.C. Cartridge Retention Enabling
Details.................................................61
Figure 27. SEC Cartridge Retention Enabling
Details.................................................62
Figure 28. Side View of Connector Mating
Details.................................................63
Figure 29. Top View of Cartridge Insertion
Pressure Points ..................................64
Figure 30. Front View of Connector Mating
Details.................................................64
Figure 31. Boxed Pentium II Xeon
Processor............................................75
Figure 32. Side View Space Requirements for
the Boxed Processor..........................76
Figure 33. Front View Space Requirements for
the Boxed Processor..........................77
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