- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II xeon processor (Intel Corp.) pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 87/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁當前第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
87
12/15/98 5:14 PM 24377002.doc
pins of all Pentium II Xeon processor system bus
agents.
9.1.6.
BCLK (I)
The BCLK (Bus Clock) signal determines the bus
frequency. All Pentium II Xeon processor system bus
agents must receive this signal to drive their outputs
and latch their inputs on the BCLK rising edge.
All external timing parameters are specified with
respect to the BCLK signal.
9.1.7.
BERR# (I/O)
The BERR# (Bus Error) signal is asserted to indicate
an unrecoverable error without a bus protocol
violation. It may be driven by all Pentium II Xeon
processor system bus agents, and must connect the
appropriate pins of all such agents, if used. However,
Pentium II Xeon processors do not observe
assertions of the BERR# signal.
BERR# assertion conditions are configurable at a
system level. Assertion options are defined by the
following options:
Enabled or disabled.
Asserted optionally for internal errors along with
IERR#.
Asserted optionally by the request initiator of a
bus transaction after it observes an error.
Asserted by any bus agent when it observes an
error in a bus transaction.
9.1.8.
BINIT# (I/O)
The BINIT# (Bus Initialization) signal may be
observed and driven by all Pentium II Xeon
processor system bus agents, and if used must
connect the appropriate pins of all such agents. If the
BINIT# driver
is
enabled
configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future information.
during
power
on
If BINIT# observation is enabled during power-on
configuration, and BINIT# is sampled asserted, all
bus state machines are reset and any data which
was in transit is lost. All agents reset their rotating ID
for bus arbitration to the state after reset, and internal
count information is lost. The L1 and L2 caches are
not affected.
If BINIT# observation is disabled during power-on
configuration, a central agent may handle an
assertion of BINIT# as appropriate to the Machine
Check Architecture (MCA) of the system.
9.1.9.
BNR# (I/O)
The BNR# (Block Next Request) signal is used to
assert a bus stall by any bus agent who is unable to
accept new bus transactions. During a bus stall, the
current
bus
owner
cannot
transactions.
issue
any
new
Since multiple agents might need to request a bus
stall at the same time, BNR# is a wire-OR signal
which must connect the appropriate pins of all
Pentium II Xeon processor system bus agents. In
order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple
drivers, BNR# is activated on specific clock edges
and sampled on specific clock edges.
9.1.10.
BP[3:2]# (I/O)
The BP[3:2]# (Breakpoint) signals are outputs from
the processor that indicate the status of breakpoints.
9.1.11.
BPM[1:0]# (I/O)
The BPM[1:0]# (Breakpoint Monitor) signals are
breakpoint and performance monitor signals. They
are outputs from the processor which indicate the
status of breakpoints and programmable counters
used for monitoring processor performance.
9.1.12.
BPRI# (I)
The BPRI# (Bus Priority Request) signal is used to
arbitrate for ownership of the Pentium II Xeon
processor system bus. It must connect the
appropriate pins of all Pentium II Xeon processor
system bus agents. Observing BPRI# active (as
asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation.
The priority agent keeps BPRI# asserted until all of
its requests are completed, then releases the bus by
deasserting BPRI#.
9.1.13.
BR0# (I/O), BR[3:1]# (I)
The BR[3:1]# (Bus Request) pins drive the
BREQ[3:0]# signals on the system. The BR[3:0]#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動處理器) |
| pentium pro processor | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復。