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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 80/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
80
12/15/98 5:14 PM 24377002.doc
Table 43. Debug Port Pinout Description and Requirements
1
Name
Pin
Description
Specification Requirement
Notes
RESET#
1
Reset signal from MP cluster
to ITP.
Terminate
2
signal properly at
the debug port
Debug port must be at the
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on the ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents if routed properly.
DBRESET#
3
Allows ITP to reset entire
target system.
Tie signal to target system
reset (recommendation: PWR
OK signal on PCIset as an
ORed input)
Pulled-up signal with the
proper resistor (see notes)
Open drain output from ITP to
the target system. It will be
held asserted for 100 ms;
capacitance needs to be
small enough to recognize
assert. The pull-up resistor
should be picked to (1) meet
VIL of target system and (2)
meet specified rise time.
TCK
5
The TAP (Test Access Port)
clock from ITP to MP cluster.
Add 1.0k
pull-up resistor to
V
CCTAP
near driver
For SMP systems, each
processor should receive a
separately buffered TCK.
Add a series termination
resistor or a Bessel filter on
each output.
Poor routing can cause
multiple clocking problems.
Should be routed to all
components in the boundary
scan.
3
Simulations should be run to
determine the proper value for
series termination or Bessel
filter.
TMS
7
Test mode select signal from
ITP to MP cluster, controls
the TAP finite state machine.
Add 1.0k
pull-up resistor to
V
CCTAP
near driver
For SMP systems, each
processor should receive a
separately buffered TMS.
Add a series termination
resistor on each output.
Operates synchronously with
TCK. Should be routed to all
components in the boundary
scan.
3
Simulations should be run to
determine the proper value for
series termination.
TDI
8
Test data input signal from
ITP to first component in
boundary scan chain of MP
cluster; inputs test
instructions and data serially.
This signal is open-drain from
the ITP. However, TDI is
pulled up to V
with
~150
on the Pentium II
Xeon processor. Add a 150
to 330
pull-up resistor (to
V
) if TDI will not be
connected directly to a
processor.
Operates synchronously with
TCK.
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