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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 89/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
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12/15/98 5:14 PM 24377002.doc
9.1.14.
D[63:00]# (I/O)
The D[63:00]# (Data) signals are the data signals.
These signals provide a 64-bit data path between the
Pentium II Xeon processor system bus agents, and
must connect the appropriate pins on all such
agents. The data driver asserts DRDY# to indicate a
valid data transfer.
9.1.15.
DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by
the agent responsible for driving data on the Pentium
II Xeon processor system bus to indicate that the
data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the
appropriate pins on all Pentium II Xeon processor
system bus agents.
9.1.16.
DEFER# (I)
The DEFER# signal is asserted by an agent to
indicate that a transaction cannot be guaranteed in-
order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or I/O
agent. This signal must connect the appropriate pins
of all Pentium II Xeon processor system bus agents.
9.1.17.
DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals
provide optional ECC protection for the data bus.
They are driven by the agent responsible for driving
D[63:00]#, and must connect the appropriate pins of
all Pentium II Xeon processor system bus agents
which use them. The DEP[7:0]# signals are enabled
or disabled for ECC protection during power on
configuration.
9.1.18.
DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the
data driver on each data transfer, indicating valid
data on the data bus. In a multicycle data transfer,
DRDY# may be deasserted to insert idle clocks. This
signal must connect the appropriate pins of all
Pentium II Xeon processor system bus agents.
9.1.19.
EMI
The EMI pins should be connected to motherboard or
chassis ground through zero ohm resisters.
9.1.20.
FERR# (O)
The FERR# (Floating-point Error) signal is asserted
when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for
compatibility with systems using MS-DOS*-type
floating-point error reporting.
9.1.21.
FLUSH# (I)
When the FLUSH# input signal is asserted,
processors write back all data in the Modified state
from their internal caches and invalidate all internal
cache lines. At the completion of this operation, the
processor issues a Flush Acknowledge transaction.
The processor does not cache any new data while
the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
On the active-to-inactive transition of RESET#, each
processor samples FLUSH# to determine its power-
on configuration. See the Pentium
II Processor
Developer’s Manual or details.
9.1.22.
FRCERR (I/O)
If two processors are configured in a Functional
Redundancy Checking (FRC) master/checker pair,
as a single “l(fā)ogical” processor, the FRCERR
(Functional Redundancy Checking Error) signal is
asserted by the checker if a mismatch is detected
between the internally sampled outputs and the
master’s outputs. The checker’s FRCERR output pin
must be connected with the master’s FRCERR input
pin in this configuration.
For point-to-point connections, the checker always
compares against the master’s outputs. For bussed
single-driver signals, the checker compares against
the signal when the master is the only allowed driver.
For bussed multiple-driver wired-OR signals, the
checker compares against the signal only if the
master is expected to drive the signal low.
When a processor is configured as an FRC checker,
FRCERR is toggled during its reset action. A checker
asserts FRCERR for approximately 1 second after
the active-to-inactive transition of RESET# if it
executes its Built-In Self-Test (BIST). When BIST
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