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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 92/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/15/98 5:14 PM 24377002.doc
BCLK
PWRGOOD
RESET#
Clock Ratio
1 ms
V
CC
L2
V ,
3770-38
Figure 38. PWRGOOD Relationship at Power-On
9.1.37.
REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must
connect the appropriate pins of all Pentium II Xeon
processor system bus agents. They are asserted by
the current bus owner over two clock cycles to define
the currently active transaction type.
9.1.38.
RESET# (I)
Asserting the RESET# signal resets all processors to
known states and invalidates their L1 and L2 caches
without writing back any of their contents. RESET#
must remain active for one microsecond for a “warm”
reset; for a power-on reset, RESET# must stay
active for at least one millisecond after V
CCCORE
and
CLK have reached their proper specifications. On
observing active RESET#, all Pentium II Xeon
processor system bus agents will deassert their
outputs within two clocks.
A number of bus signals are sampled at the active-
to-inactive transition of RESET# for power-on
configuration. These configuration options are
described in the Pentium
II Processor Developer’s
Manual
The processor may have its outputs tri-stated via
power-on configuration. Otherwise, if INIT# is
sampled active during the active-to-inactive transition
of RESET#, the processor will execute its Built-In
Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the
reset-vector (default 0_FFFF_FFF0h). RESET# must
connect the appropriate pins of all Pentium II Xeon
processor system bus agents.
9.1.39.
RP# (I/O)
The RP# (Request Parity) signal is driven by the
request initiator, and provides parity protection on
ADS# and REQ[4:0]#. It must connect the
appropriate pins of all Pentium II Xeon processor
system bus agents.
A correct parity signal is high if an even number of
covered signals are low and low if an odd number of
covered signals are low. This definition allows parity
to be high when all covered signals are high.
9.1.40.
RS[2:0]# (I)
The RS[2:0]# (Response Status) signals are driven
by the response agent (the agent responsible for
completion of the current transaction), and must
connect the appropriate pins of all Pentium II Xeon
processor system bus agents.
9.1.41.
RSP# (I)
The RSP# (Response Parity) signal is driven by the
response agent (the agent responsible for completion
of the current transaction) during assertion of
RS[2:0]#, the signals for which RSP# provides parity
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