參數(shù)資料
型號(hào): pentium II xeon processor
廠商: Intel Corp.
英文描述: pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述: 奔騰II至強(qiáng)處理器400和450兆赫(工作頻率400和450兆赫茲奔二處理器)
文件頁(yè)數(shù): 51/97頁(yè)
文件大?。?/td> 978K
代理商: PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
51
12/15/98 5:14 PM 24377002.doc
substrate. Attempting to drive either of these signals
to a Hi-Z state would cause ambiguity in the memory
device address decode, possibly resulting in the
devices not responding, thus timing out or hanging
the SMBus. As before, the “Z” bit is the read/write bit
for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are
Reserved and should not be generated by an SMBus
master.
Figure 17 shows a logical diagram of the pin
connections. Table 36 and Table 37 describe the
address pin connections and how they affect the
addressing of the devices.
Note that system management software must be
aware of the slot number-dependent changes in the
address for the thermal sensor.
Table 36. Thermal Sensor SMBus Addressing on the Pentium
II Xeon Processor
Address (Hex)
Upper Address
1
Slot Select
8-bit Address Word on Serial Bus
SA1
SA2
b[7:0]
3Xh
0011
0
0
0011000Xb
0011
1
0
0011010Xb
5Xh
0101
0
Z
2
0101001Xb
0101
1
Z
2
0101011Xb
9Xh
1001
0
1
1001100Xb
1001
1
1
1001110Xb
NOTES:
1.
2.
Upper address bits are decoded in conjunction with the select pins.
A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Table 37. Memory Device SMBus Addressing on the Pentium
II Xeon Processor
Address
(Hex)
Upper
Address
Slot Select
Memory
Device
Select
R/W
Device Addressed
bits 7-4
(SA1)
bit 3
(SA0)
bit 2
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
Scratch EEPROM 1
A2h/A3h
1010
0
0
1
X
Processor Information ROM 1
A4h/A5h
1010
0
1
0
X
Scratch EEPROM 2
A6h/A7h
1010
0
1
1
X
Processor Information ROM 2
A8h/A9h
1010
1
0
0
X
Scratch EEPROM 3
AAh/ABh
1010
1
0
1
X
Processor Information ROM 3
ACh/ADh
1010
1
1
0
X
Scratch EEPROM 4
AEh/AFh
1010
1
1
1
X
Processor Information ROM 4
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