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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 83/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
83
12/15/98 5:14 PM 24377002.doc
8.1.4.1.
General Signal Quality Notes
Signals from the debug port are fed to the system
from the ITP via a buffer board and a cable. If system
signals routed to the debug port (i.e., TDO, PRDY[x]#
and RESET#) are used elsewhere in the system,
then dedicated drivers should be used to isolate the
signals from reflections coming from the end of this
cable. If the Pentium II Xeon processor boundary
scan signals are used elsewhere in the system, then
the TDI, TMS, TCK, and TRST# signals from the
debug port should be isolated from the system
signals.
In general, no signals should be left floating. Thus,
signals going from the debug port to the processor
system should not be left floating. If they are left
floating, there may be problems when the ITP is not
plugged into the connector.
8.1.4.2.
Signal Note: DBRESET#
The DBRESET# output signal from the ITP is an
open drain with about 5
of R
DS
. The usual
implementation is to connect it to the PWROK open
drain signal on the PCIset components as an OR
input to initiate a system reset. In order for the
DBRESET# signal to work properly, it must actually
reset the entire target system. The signal should be
pulled up (Intel recommends a 240
resistor, but
system designers will need to fine tune specific
system designs) to meet two considerations: (1) the
signal must be able to meet V
IL
of the system, and
(2) it must allow the signal to meet the specified rise
time. When asserted by the ITP, the DBRESET#
signal will remain asserted for 100 ms. A large
capacitance should not be present on this signal as it
may prevent a full charge from building up within 100
ms.
8.1.4.3.
Signal Note: TDO and TDI
The TDO signal of each processor has a 2.5 V
Tolerant open-drain driver. The TDI signal of each
processor contains a 150
pull-up to V
CCTAP
. When
connecting one Pentium II Xeon processor to the
next, or connecting to the TDI of the first processor,
no external pull-up is required. However, the last
processor of the chain does require a pull-up before
passing the signal to the next device in the chain.
8.1.4.4.
Signal Note: TCK
WARNING
A significant number of target systems
have had signal integrity issues with the
TCK signal. TCK is a critical clock signal
and must be routed accordingly; make
sure to observe power and ground plane
integrity for this signal. Follow the
guidelines below and assure the quality of
the signal when beginning use of an ITP to
debug your target.
Due to the number of loads on the TCK signal,
special care should be taken when routing this signal
on the motherboard. Poor routing can lead to multiple
clocking of some agents on the debug chain. This
causes information to be lost through the chain and
can result in bad commands being issued to some
agents on the chain.
The suggested routing scheme is to drive each of the
agent TCK signals individually from a buffer device.
Figure 36 shows how the TCK signal should be
routed to the agents in a 4-way Pentium II Xeon
Processor system incorporating the Intel 450NX
PCIset. A Bessel filter is recommended over a series
termination at the output of each buffer. The values
shown in Figure 36 are only examples. The designer
should determine the LC values appropriate for their
particular application.
If it is desired to ship production systems without
the 2.5 V buffers installed, then pull-up resistors
should be placed at the outputs to prevent TCK
from floating.
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