參數(shù)資料
型號： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁數(shù)： 10/97頁
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
10
12/15/98 5:14 PM 24377002.doc
Pentium Pro processor in its output buffer
implementation. The buffers that drive most of the
system bus signals on the Pentium II Xeon
processor are actively driven to V
CCCORE
for one
clock cycle after the low to high transition to
improve rise-times and reduce noise. These signals
should still be considered open-drain and require
termination to a supply that provides the high signal
level. Because this specification is different from the
standard GTL+ specification, it is referred to as
Assisted Gunning Transistor Logic (AGTL+) in this
document. AGTL+ logic and GTL+ logic are
compatible with each other and may both be used
on the same system bus. For more information on
the GTL+ specification, see the Pentium
Pro
Family Developer’s Manual, Volume I.
AGTL+ inputs use differential receivers which
require a reference signal (V
REF
). V
REF
is used by
the receivers to determine if a signal is a logical 0 or
a logical 1. The Pentium II Xeon processor
generates its own version of V
REF
. V
REF
must be
generated on the motherboard for other devices on
the AGTL+ system bus. Termination is used to pull
the bus up to the high voltage level and to control
signal integrity on the transmission line. The
processor contains termination resistors that
provide termination for each Pentium II Xeon
processor. These specifications assume the
equivalent of 6 AGTL+ loads and termination
resistors to ensure the proper timings on rising and
falling edges. See test conditions described with
each specification.
Due to the existence of termination on each of up to
4 processors in a Pentium II Xeon processor
system, the AGTL+ bus is typically not a daisy
chain topology as in previous P6 family processor
systems. Also new to Pentium II Xeon processors,
timing specifications are defined to points internal to
the
processor
packaging.
simulation of the system bus is required
when
developing Pentium II Xeon processor based
systems to ensure proper operation over all
conditions. Pentium
II Xeon Processor I/O Buffer
Models are available for simulation.
Analog
signal
The 100 MHz 2-Way SMP Pentium
II Xeon
Processor/Intel
440GX AGPset AGTL+ Layout
Guidelines and Pentium
II Xeon Processor/Intel
450NX PCIset AGTL+ Layout Guidelines contains
information on possible layout topologies and other
information for analog simulation.
2.2.
Power and Ground Pins
The operating voltage of the processor die and of
the L2 cache die differ from each other. There are
two groups of power inputs on the Pentium II Xeon
processor package to
difference between the components in the package.
There are also five pins defined on the package for
core voltage identification (VID_CORE), and five
pins defined on the package for L2 cache voltage
identification (VID_L2). These pins specify the
voltage required by the processor core and L2
cache respectively. These have been added to
cleanly support voltage specification variations on
current and future Pentium II Xeon processors.
support
this
voltage
For signal integrity improvement and clean power
distribution within the S.E.C. package, Pentium II
Xeon processors have 67 V
CC
(power) and 56 V
SS
(ground) inputs. The 67 V
CC
pins are further divided
to provide the different voltage levels to the
components. V
CCCORE
inputs for the processor core
account for 35 of the V
CC
pins, while 8 V
TT
inputs
(1.5 V) are used to provide an AGTL+ termination
voltage to the processor and 20 V
CCL2
inputs are for
use by the L2 cache. One V
CCSMBUS
pin is provided
for use by the SMBus and one V
CCTAP
.for the test
access port. V
CCSMBUS
, V
CCL2
, and V
CCCORE
must
remain electrically separated from each other. On
the circuit board, all V
CCCORE
pins must be
connected to a voltage island and all V
CCL2
pins
must be connected to a separate voltage island (an
island is a portion of a power plane that has been
divided, or an entire plane). Similarly, all V
SS
pins
must be connected to a system ground plane.
2.3.
Decoupling Guidelines
Due to the large number of transistors and high
internal clock speeds, the processor is capable of
generating large average current swings between
low and full power states. This causes voltages on
power planes to sag below their nominal values if
bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage
provided to the processor remains within the
specifications listed in Table 5. Failure to do so can
result in timing violations or a reduced lifetime of the
component.
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