參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 45/97頁(yè)
文件大小： 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
45
12/15/98 5:14 PM 24377002.doc
Table 23. Processor Information ROM Format
(Continued)
32
Cartridge Feature Flags
[6] = Serial Signature
[5] = Electronic Signature Present
[4] = Thermal Sense Device Present
[3] = Thermal Reference Byte
Present
[2] = OEM EEPROM Present
[1] = Core VID Present
[0] = L2 Cache VID Present
4
Number of Devices in TAP Chain
One 4-bit hex digit
4
Reserved
Reserved for future use
8
Checksum
1 byte checksum
OTHER: 7Eh
16
Reserved
Reserved for future use
4.3.2.
SCRATCH EEPROM
Also available on the SMBus is an EEPROM which
may be used for other data at the system or
processor vendor’s discretion. The data in this
EEPROM, once programmed, can be write-protected
by asserting the active-high WP signal. This signal
has a weak pull-down (10k
) to allow the EEPROM
to be programmed in systems with no implementation
of this signal. The Scratch EEPROM is a 1024 bit
part.
4.3.3.
PROCESSOR INFORMATION ROM
AND SCRATCH EEPROM
SUPPORTED SMBUS TRANSACTIONS
The Processor Information ROM responds to three
SMBus packet types: current address read, random
address read, and sequential read. The Scratch
EEPROM responds to two additional packet types:
byte write and page write. Table 24 diagrams the
current address read. The internal address counter
keeps track of the address accessed during the last
read or write operation, incremented by one. Address
“roll over” during reads is from the last byte of the last
eight byte page to the first byte of the first page. “Roll
over” during writes is from the last byte of the current
eight byte page to the first byte of the same page.
Table 25 diagrams the random read. The write with
no data loads the address desired to be read.
Sequential reads may begin with a current address
read or a random address read. After the SMBus
host controller receives the data word it responds
with an acknowledge. This will continue until the
SMBus host controller responds with a negative
acknowledge and a stop. Table 26 diagrams the byte
write. The page write operates the same way as the
byte write except that the SMBus host controller
does not send a stop after the first data byte and
acknowledge. The Scratch EEPROM internally
increments its address. The SMBus host controller
continues to transmit data bytes until it terminates the
sequence with a stop. All data bytes will result in an
acknowledge from the Scratch EEPROM. If more
than eight bytes are written the internal address will
“roll over” and the previous data will be overwritten.
In the tables, ‘S’ represents the SMBus start bit, ‘P’
represents a stop bit, ‘R’ represents a read bit, ‘W’
represents
a
write
bit,
acknowledge, and ‘///’ represents a negative
acknowledge. The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM
and the bits that aren’t shaded are transmitted by the
SMBus host controller. In the tables the data
addresses indicate 8 bits. The SMBus host controller
should transmit 8 bits, but as there are only 128
addresses, the most significant bit is a don’t care.
‘A’
represents
an
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