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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 19/97頁 |
| 文件大小： | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
19
12/15/98 5:14 PM 24377002.doc
Table 4. Pentium
II Xeon Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
T
STORAGE
Processor storage temperature
–40
85
°C
V
CCCORE
Processor core supply voltage
with respect to V
SS
–0.5
Operating voltage + 1.0
V
1
V
CCL2
Any processor L2 supply
voltage with respect to V
SS
–0.5
Operating voltage + 1.0
V
1
V
SMBus
Any processor SM supply
voltage with respect to V
SS
-0.3
Operating voltage + 1.0
V
V
CCTAP
Any processor TAP supply
voltage with respect to V
SS
-0.3
3.3
V
1
V
CCL2
-
V
CCCORE
L2 supply voltage with respect
to core voltage.
-(Core
Operating
Voltage)
L2 Operating Voltage
V
1, 2
V
inGTL
AGTL+ buffer DC input voltage
with respect to V
SS
–0.3
V
CCCORE
+ 0.7
V
V
inCMOS
CMOS & APIC buffer DC input
voltage with respect to V
SS
–0.3
3.3
V
V
inSMBus
SMBus buffer DC input voltage
with respect to V
SS
-0.1
6.0
V
I
PWR_EN
Max PWR_EN[1:0] pin current
100
mA
I
VID
Max VID pin current
5
mA
NOTES:
1.
2.
Operating voltage is the voltage to which the component is designed to operate. See Table 5.
This parameter specifies that the processor will not be immediately damaged by either supply being disabled.
2.10.
Processor DC Specifications
The voltage and current specifications provided in
Table 5 and Table 6 are defined at the processor
edge fingers. The processor signal DC specifications
in Table 7, Table 8, and Table 9 are defined at the
Pentium II Xeon processor core. Each signal trace
between the processor edge finger and the
processor core carries a small amount of current and
has a finite resistance. The current produces a
voltage drop between the processor edge finger and
the core. Simulations should therefore be run versus
these specifications to the processor core.
See Section 9.0. for the processor edge finger signal
definitions and Table 3 for the signal grouping.
Most of the signals on the Pentium II Xeon processor
system bus are in the AGTL+ signal group. These
signals are specified to be terminated to V
TT
. The DC
specifications for these signals are listed in Table 7.
To ease connection with other devices, the Clock,
CMOS, APIC, SMBus and TAP signals are designed
to interface at non-AGTL+ levels. The DC
specifications for these pins are listed in Table 8 and
Table 9.
NOTE
Unless otherwise noted, each specification
applies to all Pentium II Xeon processors.
Where differences exist between Pentium II
Xeon processors, look for the table entries
identified by “
FMB
” in order to design a
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