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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 90/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/15/98 5:14 PM 24377002.doc
execution
deasserts FRCERR if BIST completed successfully,
and continues to assert FRCERR if BIST fails. If the
checker processor does not execute the BIST action,
then it keeps FRCERR asserted for approximately 20
clocks and then deasserts it.
completes,
the
checker
processor
All asynchronous signals must be externally
synchronized to BCLK by system logic during FRC
mode operation.
9.1.23.
HIT# (I/O), HITM# (I/O)
The HIT# (Snoop Hit) and HITM# (Hit Modified)
signals convey transaction snoop operation results,
and must connect the appropriate pins of all Pentium
II Xeon processor system bus agents. Any such
agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
9.1.24.
IERR# (O)
The IERR# (Internal Error) signal is asserted by a
processor as the result of an internal error. Assertion
of IERR# is usually accompanied by a SHUTDOWN
transaction on the Pentium II Xeon processor system
bus. This transaction may optionally be converted to
an external error signal (e.g., NMI) by system core
logic. The processor will keep IERR# asserted until it
is handled in software, or with the assertion of
RESET#, BINIT#, or INIT#.
9.1.25.
IGNNE# (I)
The IGNNE# (Ignore Numeric Error) signal is
asserted to force the processor to ignore a numeric
error and continue to execute noncontrol floating-
point instructions. If IGNNE# is deasserted, the
processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point
instruction caused an error. IGNNE# has no effect
when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
During active RESET#, the Pentium II Xeon
processor begins sampling the A20M#, IGNNE#, and
LINT[1:0] values to determine the ratio of core-clock
frequency to bus-clock frequency. See Table 1. On
the active-to-inactive transition of RESET#, the
Pentium II Xeon processor latches these signals and
freezes the frequency ratio internally. System logic
must then release these signals for normal operation.
9.1.26.
INIT# (I)
The INIT# (Initialization) signal, when asserted,
resets integer registers inside all processors without
affecting their internal (L1 or L2) caches or floating-
point registers. Each processor then begins
execution at the power-on reset vector configured
during power-on configuration. The processor
continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all Pentium II Xeon
processor system bus agents.
If INIT# is sampled active on the active to inactive
transition of RESET#, then the processor executes
its Built-In Self-Test (BIST).
9.1.27.
INTR -
SEE LINT[0]
9.1.28.
LINT[1:0] (I)
The LINT[1:0] (Local APIC Interrupt) signals must
connect the appropriate pins of all APIC Bus agents,
including all processors and the core logic or I/O
APIC component. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt
request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured
via BIOS programming of the APIC register space to
be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after reset, operation
of these pins as LINT[1:0] is the default configuration.
During active RESET#, the Pentium II Xeon
processor begins sampling the A20M#, IGNNE#, and
LINT[1:0] values to determine the ratio of core-clock
frequency to bus-clock frequency. See Table 1. On
the active-to-inactive transition of RESET#, the
Pentium II Xeon processor samples these signals
and latches the frequency ratio internally. System
logic must then release these signals for normal
operation.
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