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參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 9/56頁 |
| 文件大小： | 689K |
| 代理商： | NS32490D |
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7.0 Packet Reception
(Continued)
Received Packet Aborted if It Hits Boundary Pointer
TL/F/8582–8
Buffer Ring Overflow
If the Buffer Ring has been filled and the DMA reaches the
Boundary Pointer Address, reception of the incoming pack-
et will be aborted by the NIC. Thus, the packets previously
received and still contained in the Ring will not be de-
stroyed.
In a heavily loaded network environment the local DMA may
be disabled, preventing the NIC from buffering packets from
the network. To guarantee this will not happen, a software
reset must be issued during all Receive Buffer Ring over-
flows (indicated by the OVW bit in the Interrupt Status Reg-
ister).
The following procedure is required to recover
from a Receiver Buffer Ring Overflow.
If this routine is not adhered to, the NIC may act in an unpre-
dictable manner. It should also be noted that it is not per-
missible to service an overflow interrupt by continuing to
empty packets from the receive buffer without implementing
the prescribed overflow routine. A flow chart of the NIC’s
overflow routine can be found at the right.
Note:
It is necessary to define a variable in the driver, which will be called
‘‘Resend’’.
1. Read and store the value of the TXP bit in the NIC’s
Command Register.
2. Issue the STOP command to the NIC. This is accom-
plished be setting the STP bit in the NIC’s Command
Register. Writing 21H to the Command Register will stop
the NIC.
Note:
If the STP is set when a transmission is in progress, the RST bit may
not be set. In this case, the NIC is guaranteed to be reset after the
longest packet time (1500 bytes
e
1.2 ms). For the DP8390D (but not
for the DP8390B), the NIC will be reset within 2 microseconds after
the STP bit is set and Loopback mode 1 is programmed.
3. Wait for at least 1.6 ms. Since the NIC will complete any
transmission or reception that is in progress, it is neces-
sary to time out for the maximum possible duration of an
Ethernet transmission or reception. By waiting 1.6 ms this
is achieved with some guard band added. Previously, it
was recommended that the RST bit of the Interrupt
Status Register be polled to insure that the pending
transmission or reception is completed. This bit is not a
reliable indicator and subsequently should be ignored.
4. Clear the NIC’s Remote Byte Count registers (RBCR0
and RBCR1).
TL/F/8582–95
Overflow Routine Flow Chart
5. Read the stored value of the TXP bit from step 1, above.
If this value is a 0, set the ‘‘Resend’’ variable to a 0 and
jump to step 6.
If this value is a 1, read the NIC’s Interrupt Status Regis-
ter. If either the Packet Transmitted bit (PTX) or Trans-
mit Error bit (TXE) is set to a 1, set the ‘‘Resend’’ vari-
able to a 0 and jump to step 6. If neither of these bits is
set, place a 1 in the ‘‘Resend’’ variable and jump to step
6.
This step determines if there was a transmission in prog-
ress when the stop command was issued in step 2. If
there was a transmission in progress, the NIC’s ISR is
read to determine whether or not the packet was recog-
nized by the NIC. If neither the PTX nor TXE bit was set,
9
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