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參數(shù)資料
| 型號(hào)： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 1/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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TL/F/8582
D
July 1995
DP8390D/NS32490D NIC Network Interface Controller
General Description
The DP8390D/NS32490D Network Interface Controller
(NIC) is a microCMOS VLSI device designed to ease inter-
facing with CSMA/CD type local area networks including
Ethernet, Thin Ethernet (Cheapernet) and StarLAN. The
NIC implements all Media Access Control (MAC) layer func-
tions for transmission and reception of packets in accord-
ance with the IEEE 802.3 Standard. Unique dual DMA chan-
nels and an internal FIFO provide a simple yet efficient
packet management design. To minimize system parts
count and cost, all bus arbitration and memory support logic
are integrated into the NIC.
The NIC is the heart of a three chip set that implements the
complete IEEE 802.3 protocol and node electronics as
shown below. The others include the DP8391 Serial Net-
work Interface (SNI) and the DP8392 Coaxial Transceiver
Interface (CTI).
Features
Y
Compatible with IEEE 802.3/Ethernet II/Thin Ethernet/
StarLAN
Y
Interfaces with 8-, 16- and 32-bit microprocessor
systems
Y
Implements simple, versatile buffer management
Y
Requires single 5V supply
Y
Utilizes low power microCMOS process
Y
Includes
D Two 16-bit DMA channels
D 16-byte internal FIFO with programmable threshold
D Network statistics storage
Y
Supports physical, multicast, and broadcast address
filtering
Y
Provides 3 levels of loopback
Y
Utilizes independent system and network clocks
Table of Contents
1.0 SYSTEM DIAGRAM
2.0 BLOCK DIAGRAM
3.0 FUNCTIONAL DESCRIPTION
4.0 TRANSMIT/RECEIVE PACKET ENCAPSULATION/
DECAPSULATION
5.0 PIN DESCRIPTIONS
6.0 DIRECT MEMORY ACCESS CONTROL (DMA)
7.0 PACKET RECEPTION
8.0 PACKET TRANSMISSION
9.0 REMOTE DMA
10.0 INTERNAL REGISTERS
11.0 INITIALIZATION PROCEDURES
12.0 LOOPBACK DIAGNOSTICS
13.0 BUS ARBITRATION AND TIMING
14.0 PRELIMINARY ELECTRICAL CHARACTERISTICS
15.0 SWITCHING CHARACTERISTICS
16.0 PHYSICAL DIMENSIONS
1.0 System Diagram
IEEE 802.3 Compatible Ethernet/Thin Ethernet Local Area Network Chip Set
TL/F/8582–1
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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