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參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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10.0 Internal Registers
(Continued)
10.3 Register Descriptions
(Continued)
DATA CONFIGURATION REGISTER (DCR)
0EH (WRITE)
This Register is used to program the NIC for 8- or 16-bit memory interface, select byte ordering in 16-bit applications and
establish FIFO threshholds.
The DCR must be initialized prior to loading the Remote Byte Count Registers. LAS is set on
power up.
7
6
5
4
3
2
1
0
D
FT1
FT0
ARM
LS
LAS
BOS
WTS
Bit
Symbol
Description
D0
WTS
WORD TRANSFER SELECT
0: Selects byte-wide DMA transfers
1: Selects word-wide DMA transfers
; WTS establishes byte or word transfers
for both Remote and Local DMA transfers
Note:
When word-wide mode is selected, up to 32k words are addressable; A0 remains low.
D1
BOS
BYTE ORDER SELECT
0: MS byte placed on AD15–AD8 and LS byte on AD7–AD0. (32000, 8086)
1: MS byte placed on AD7–AD0 and LS byte on AD15–AD8. (68000)
; Ignored when WTS is low
D2
LAS
LONG ADDRESS SELECT
0: Dual 16-bit DMA mode
1: Single 32-bit DMA mode
; When LAS is high, the contents of the Remote DMA registers RSAR0,1 are issued as A16–A31
Power up high.
D3
LS
LOOPBACK SELECT
0: Loopback mode selected. Bits D1, D2 of the TCR must also be programmed for Loopback
operation.
1: Normal Operation.
D4
AR
AUTO-INITIALIZE REMOTE
0: Send Command not executed, all packets removed from Buffer Ring under program control.
1: Send Command executed, Remote DMA auto-initialized to remove packets from Buffer Ring.
Note:
Send Command cannot be used with 68000 type processors.
D5, D6
FT0, FT1
FIFO THRESHHOLD SELECT:
Encoded FIFO threshhold. Establishes point at which bus is
requested when filling or emptying the FIFO. During reception, the FIFO threshold indicates the
number of bytes (or words) the FIFO has filled serially from the network before bus request
(BREQ) is asserted.
Note:
FIFO threshold setting determines the DMA burst length.
RECEIVE THRESHOLDS
FT1
FT0
Word Wide
0
0
1 Word
0
1
2 Words
1
0
4 Words
1
1
6 Words
During transmission, the FIFO threshold indicates the numer of bytes (or words) the FIFO has
filled from the Local DMA before BREQ is asserted. Thus, the transmission threshold is 16 bytes
less the receive threshold.
Byte Wide
2 Bytes
4 Bytes
8 Bytes
12 Bytes
22
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