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參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 6/56頁 |
| 文件大小： | 689K |
| 代理商： | NS32490D |
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5.0 Pin Descriptions
(Continued)
BUS INTERFACE PINS
(Continued)
Symbol
DIP Pin No
Function
Description
PWR
27
O
PORT WRITE:
Strobe used to latch data from the NIC into external latch for
transfer to host memory during Remote Read transfers. The rising edge of PWR
coincides with the presence of valid data on the local bus.
RACK
26
I
READ ACKNOWLEDGE:
Indicates that the system DMA or host CPU has read
the data placed in the external latch by the NIC. The NIC will begin a read cycle
to update the latch.
BSCK
25
I
This clock is used to establish the period of the DMA memory cycle. Four clock
cycles (t1, t2, t3, t4) are used per DMA cycle. DMA transfers can be extended by
one BSCK increments using the READY input.
NETWORK INTERFACE PINS
COL
40
I
COLLISION DETECT:
This line becomes active when a collision has been
detected on the coaxial cable. During transmission this line is monitored after
preamble and synch have been transmitted. At the end of each transmission this
line is monitored for CD heartbeat.
RXD
39
I
RECEIVE DATA:
Serial NRZ data received from the ENDEC, clocked into the
NIC on the rising edge of RXC.
CRS
38
I
CARRIER SENSE:
This signal is provided by the ENDEC and indicates that
carrier is present. This signal is active high.
RXC
37
I
RECEIVE CLOCK:
Re-synchronized clock from the ENDEC used to clock data
from the ENDEC into the NIC.
LBK
35
O
LOOPBACK:
This output is set high when the NIC is programmed to perform a
loopback through the StarLAN ENDEC.
TXD
34
O
TRANSMIT DATA:
Serial NRZ Data output to the ENDEC. The data is valid on
the rising edge of TXC.
TXC
33
I
TRANSMIT CLOCK:
This clock is used to provide timing for internal operation
and to shift bits out of the transmit serializer. TXC is nominally a 1 MHz clock
provided by the ENDEC.
TXE
32
O
TRANSMIT ENABLE:
This output becomes active when the first bit of the
packet is valid on TXD and goes low after the last bit of the packet is clocked out
of TXD. This signal connects directly to the ENDEC. This signal is active high.
POWER
V
CC
36
a
5V DC is required. It is suggested that a decoupling capacitor be connected
between these pins. It is essential to provide a path to ground for the GND pin
with the lowest possible impedance.
GND
13
6.0 Direct Memory Access Control (DMA)
The DMA capabilities of the NIC greatly simplify use of the
DP8390D in typical configurations. The local DMA channel
transfers data between the FIFO and memory. On transmis-
sion, the packet is DMA’d from memory to the FIFO in
bursts. Should a collision occur (up to 15 times), the packet
is retransmitted with no processor intervention. On recep-
tion, packets are DMAed from the FIFO to the receive buffer
ring (as explained below).
A remote DMA channel is also provided on the NIC to ac-
complish transfers between a buffer memory and system
memory. The two DMA channels can alternatively be com-
bined to form a single 32-bit address with 8- or 16-bit data.
DUAL DMA CONFIGURATION
An example configuration using both the local and remote
DMA channels is shown below. Network activity is isolated
on a local bus, where the NIC’s local DMA channel per-
forms burst transfers between the buffer memory and the
NIC’s FIFO. The Remote DMA transfers data between the
buffer memory and the host memory via a bidirectional I/O
port. The Remote DMA provides local addressing capability
and is used as a slave DMA by the host. Host side address-
ing must be provided by a host DMA or the CPU. The NIC
allows Local and Remote DMA operations to be interleaved.
SINGLE CHANNEL DMA OPERATION
If desirable, the two DMA channels can be combined to
provide a 32-bit DMA address. The upper 16 bits of the 32-
bit address are static and are used to point to a 64k byte (or
32k word) page of memory where packets are to be re-
ceived and transmitted.
6
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