參數(shù)資料
型號(hào)： NS32490D
廠商： National Semiconductor Corporation
英文描述： NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器)
中文描述： NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器）
文件頁(yè)數(shù)： 35/56頁(yè)
文件大?。?/td> 689K
代理商： NS32490D
13.0 Bus Arbitration and Timing
(Continued)
When in 32-bit mode four additional BSCK cycles are re-
quired per burst. The first bus cycle (T1
ê
–T4
ê
) of each burst
is used to output the upper 16-bit addresses. This 16-bit
address is programmed in RSAR0 and RSAR1 and points to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.
FIFO BURST CONTROL
All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will
transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If BACK is
removed during the transfer, the burst transfer will be abort-
ed.
(DROPPING BACK DURING A DMA CYCLE IS NOT
RECOMMENDED.)
TL/F/8582–69
where N
e
1, 2, 4, or 6 Words or N
e
2, 4, 8, or 12 Bytes when in byte mode
INTERLEAVED LOCAL OPERATION
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA
transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:
TL/F/8582–70
Note that if the FIFO requires service while a remote DMA is
in progress, BREQ is not dropped and the Local DMA burst
is appended to the Remote Transfer. When switching from
a local transfer to a remote transfer, however, BREQ is
dropped and raised again. This allows the CPU or other
devices to fairly contend for the bus.
REMOTE DMA-BIDIRECTIONAL PORT CONTROL
The Remote DMA transfers data between the local buffer
memory and a bidirectional port (memory to I/O transfer).
This transfer is arbited on a byte by byte basis versus the
burst transfer used for Local DMA transfers. This bidirec-
tional port is also read/written by the host. All transfers
through this port are asynchronous. At any one time trans-
fers are limited to one direction, either from the port to local
buffer memory (Remote Write) or from local buffer memory
to the port (Remote Read).
Bus Handshake Signals for Remote DMA Transfers
TL/F/8582–71
35
相關(guān)PDF資料
PDF描述
NS32828 1 Megabit High Speed Dynamic RAM Controller/Drivers
NS32829 1 Megabit High Speed Dynamic RAM Controller/Drivers
NS32FX16-15 FILM/M CAPACITANCE=0.001 VOLT=630
NS32FX16-20 Imaging/Signal Processor
NS32FX16-25 Imaging/Signal Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32491 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Serial Network Interface
NS32491A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
NS32492B 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Coaxial Transceiver Interface
NS32532-20 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
NS32532-25 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
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