參數(shù)資料
型號: NS32490D
廠商: National Semiconductor Corporation
英文描述: NIC Network Interface Controller(NIC網(wǎng)絡接口控制器)
中文描述: NIC網(wǎng)絡接口控制器(NIC網(wǎng)絡接口控制器)
文件頁數(shù): 4/56頁
文件大?。?/td> 689K
代理商: NS32490D
Connection Diagrams
Plastic Chip Carrier
TL/F/8582–5
Dual-In-Line Package
TL/F/8582–4
Order Number DP8390DN or DP8390DV
See NS Package Number N48A or V68A
5.0 Pin Descriptions
BUS INTERFACE PINS
Symbol
DIP Pin No
Function
Description
AD0–AD15
1–12
14–17
I/O,Z
MULTIPLEXED ADDRESS/DATA BUS:
#
Register Access, with DMA inactive, CS low and ACK returned from NIC, pins
AD0–AD7 are used to read/write register data. AD8–AD15 float during I/O
transfers. SRD, SWR pins are used to select direction of transfer.
#
Bus Master with BACK input asserted.
During t1 of memory cycle AD0–AD15 contain address.
During t2, t3, t4 AD0–AD15 contain data (word transfer mode).
During t2, t3, t4 AD0–AD7 contain data, AD8–AD15 contain address
(byte transfer mode).
Direction of transfer is indicated by NIC on MWR, MRD lines.
ADS0
18
I/O,Z
ADDRESS STROBE 0
#
Input with DMA inactive and CS low, latches RA0–RA3 inputs on falling edge.
If high, data present on RA0–RA3 will flow through latch.
#
Output when Bus Master, latches address bits (A0–A15) to external memory
during DMA transfers.
4
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