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參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 12/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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8.0 Packet Transmission
(Continued)
TRANSMISSION
Prior to transmission, the TPSR (Transmit Page Start Regis-
ter) and TBCR0, TBCR1 (Transmit Byte Count Registers)
must be initialized. To initiate transmission of the packet the
TXP bit in the Command Register is set. The Transmit
Status Register (TSR) is cleared and the NIC begins to pre-
fetch transmit data from memory (unless the NIC is currently
receiving). If the interframe gap has timed out the NIC will
begin transmission.
CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet, the following three conditions
must be met:
1. The Interframe Gap Timer has timed out the first 6.4
m
s
of the Interframe Gap (See appendix for Interframe Gap
Flowchart)
2. At least one byte has entered the FIFO. (This indicates
that the burst transfer has been started)
3. If the NIC had collided, the backoff timer has expired.
In typical systems the NIC has already prefetched the first
burst of bytes before the 6.4
m
s timer expires. The time
during which NIC transmits preamble can also be used to
load the FIFO.
Note:
If carrier sense is asserted before a byte has been loaded into the
FIFO, the NIC will become a receiver.
COLLISION RECOVERY
During transmission, the Buffer Management logic monitors
the transmit circuitry to determine if a collision has occurred.
If a collision is detected, the Buffer Management logic will
reset the FIFO and restore the Transmit DMA pointers for
retransmission of the packet. The COL bit will be set in the
TSR and the NCR (Number of Collisions Register) will be
incremented. If 15 retransmissions each result in a collision
the transmission will be aborted and the ABT bit in the TSR
will be set.
Note:
NCR reads as zeroes if excessive collisions are encountered.
TRANSMIT PACKET ASSEMBLY FORMAT
The following diagrams describe the format for how packets
must be assembled prior to transmission for different byte
ordering schemes. The various formats are selected in the
Data Configuration Register.
D15
D8 D7
D0
DA1
DA0
DA3
DA2
DA5
DA4
SA1
DA0
SA3
DA2
SA5
DA4
T/L1
T/L0
DATA 1
DATA 0
BOS
e
0, WTS
e
1 in Data Configuration Register.
This format is used with Series 32000, 808X type proces-
sors.
D15
D8 D7
D0
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
SA2
SA3
SA4
SA5
T/L0
T/L1
DATA 0
DATA 1
BOS
e
1, WTS
e
1 in Data Configuration Register.
This format is used with 68000 type processors.
D7
D0
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
SA2
SA3
BOS
e
0, WTS
e
0 in Data Configuration Register.
This format is used with general 8-bit CPUs.
Note:
All examples above will result in a transmission of a packet in order of
DA0, DA1, DA2, DA3 . . . bits within each byte will be transmitted least
significant bit first.
DA
e
Destination Address
SA
e
Source Address
T/L
e
Type/Length Field
9.0 Remote DMA
The Remote DMA channel is used to both assemble pack-
ets for transmission, and to remove received packets from
the Receive Buffer Ring. It may also be used as a general
purpose slave DMA channel for moving blocks of data or
commands between host memory and local buffer memory.
There are three modes of operation, Remote Write, Remote
Read, or Send Packet.
Two register pairs are used to control the Remote DMA, a
Remote Start Address (RSAR0, RSAR1) and a Remote
Byte Count (RBCR0, RBCR1) register pair. The Start Ad-
dress Register pair points to the beginning of the block to be
moved while the Byte Count Register pair is used to indicate
the number of bytes to be transferred. Full handshake logic
is provided to move data between local buffer memory and
a bidirectional I/O port.
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