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參數(shù)資料
| 型號： | NS32828 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅動器 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32828 |
TL/F/8649
D
1
September 1991
DP8428/NS32828, DP8429/NS32829
1 Megabit High Speed Dynamic RAM Controller/Drivers
General Description
The DP8428 and DP8429 1M DRAM Controller/Drivers are
designed to provide ‘‘No-Waitstate’’ CPU interface to Dy-
namic RAM arrays of up to 8 Mbytes and larger. The
DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-
tem requirements, respectively. Both devices are fabricated
using National’s new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed, level of integration, and power
consumption.
Each device integrates the following critical 1M DRAM con-
troller functions on a single monolithic device: ultra precise
delay line; 9 bit refresh counter; fall-through row, column,
and bank select input latches; Row/Column address mux-
ing logic; on-board high capacitive-load RAS, CAS, Write
Enable and Address output drivers; and, precise control sig-
nal timing for all the above.
In order to specify each device for ‘‘true’’ worst case operat-
ing conditions, all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance. The chip’s delay timing logic makes
use of a patented new delay line technique which keeps AC
skew to
g
3 ns over the full V
CC
range of
g
10% and tem-
perature range of
b
55
§
C to
a
125
§
C. The DP8428 and
DP8429 guarantee a maximum RASIN to CASOUT delay of
80 ns or 70 ns even while driving an 8 Mbyte memory array
with error correction check bits included. Two speed select-
ed options of these devices are shown in the switching
characteristics section of this document.
(Continued)
Features
Y
Makes DRAM interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Y
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Y
Eliminates 20 discrete components for significant board
real estate reduction, system power savings and the
elimination of chip-to-chip AC skewing
Y
On-board ultra precise delay line
Y
On-board high capacitive RAS, CAS, WE and Address
drivers (specified driving 88 DRAMs directly)
Y
AC specified for directly addressing up to 8 Mbytes
Y
Low power/high speed bipolar oxide isolated process
Y
Downward pin and function compatible with 256k
DRAM Controller/Drivers DP8409A, DP8417, DP8418,
and DP8419
Contents
Y
System and Device Block Diagrams
Y
Recommended Companion Components
Y
Device Connection Diagrams and Pin Definitions
Y
Device DifferencesDDP8428 vs DP8429
Y
Mode of Operation
(Descriptions and Timing Diagrams)
Y
Application Description and Diagrams
Y
DC/AC Electrical Specifications, Timing Diagrams and
Test Conditions
System Diagram
TL/F/8649–1
TRI-STATE
é
is a registered trademark of National Semiconductor Corp.
PAL
é
is a registered trademark of and used under license with Monolithic Memories, Inc.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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