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參數(shù)資料
| 型號： | NS32828 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機(jī)存儲器的高速控制器/驅(qū)動器 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32828 |
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Switching Characteristics
All A. C. parameters are specified with the equivalent load
capacitances, including traces, of 88 DRAMs organized as 4
banks of 22 DRAMs each. Maximums are based on worst-
case conditions including all outputs switching simulta-
neously. This, in many cases, results in the AC valves
shown in the DP84XX DRAM controller data sheet being
much looser than true worst case maximum AC delays. The
system designer should estimate the DP8429 load in his/
her application, and modify the appropriate A. C. parame-
ters using the graph inFigure 10. Two example calculations
are provided below.
TL/F/8649–28
FIGURE 10. Change in Propagation Delay
relative to ‘‘true’’ (application) load minus
AC specified data sheet load
Examples
1)
A mode 4 user driving 2 banks of DRAM has the follow-
ing loading conditions:
CAS
- 300 pF
Q0–Q9 - 250 pF
RAS
- 150 pF
A.C. parameters should be adjusted in accordance withFig-
ure 10 and the specifications given for the 88 DRAM load as
follows:
max t
RPDL
e
20 ns
b
0 ns
e
20 ns (since RAS load-
ing is the same as that which is spec’ed)
max t
CPDL
e
32 ns
b
7 ns
e
25 ns
max t
CCAS
e
46 ns
b
7 ns
e
39 ns
max t
RCC
e
41 ns
b
6 ns
e
35 ns
min t
RHA
is not significantly effected since it does not
involve an output transition
Other parameters are adjusted in a similar manner.
2)
A mode 5 user driving one bank of DRAM has the
following loading conditions:
CAS - 120 pF
Q0–Q9 - 100 pF
RAS - 120 pF
A. C. parameters should be adjusted as follows:
with RAHS
e
‘‘1’’,
max t
RICL
e
70 ns
b
11 ns
e
59 ns
max t
RCDL
e
55 ns
a
1 ns
b
11 ns
e
45 ns
(the
a
1 ns is due to lighter RAS loading; the
b
11 ns
is due to lighter CAS loading)
min t
RAH
e
15 ns
a
1 ns
e
16 ns
The additional 1 ns is due to the fact that the RAS line
is driving less (switching faster) than the load to which
the 15 ns spec applies. The row address will remain
valid for about the same time irregardless of address
loading since it is considered to be not valid at the
beginning of its transition.
TL/F/8649–29
FIGURE 11. Output Load Circuit
19
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