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參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡接口控制器) |
| 中文描述： | NIC網(wǎng)絡接口控制器（NIC網(wǎng)絡接口控制器） |
| 文件頁數(shù)： | 5/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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5.0 Pin Descriptions
(Continued)
BUS INTERFACE PINS
(Continued)
Symbol
DIP Pin No
Function
Description
CS
19
I
CHIP SELECT:
Chip Select places controller in slave mode for
m
P access to
internal registers. Must be valid through data portion of bus cycle. RA0–RA3 are
used to select the internal register. SWR and SRD select direction of data
transfer.
MWR
20
O,Z
MASTER WRITE STROBE:
Strobe for DMA transfers, active low during write
cycles (t2, t3, tw) to buffer memory. Rising edge coincides with the presence of
valid output data. TRI-STATE
é
until BACK asserted.
MRD
21
O,Z
MASTER READ STROBE:
Strobe for DMA transfers, active during read cycles
(t2, t3, tw) to buffer memory. Input data must be valid on rising edge of MRD.
TRI-STATE until BACK asserted.
SWR
22
I
SLAVE WRITE STROBE:
Strobe from CPU to write an internal register selected
by RA0–RA3.
SRD
23
I
SLAVE READ STROBE:
Strobe from CPU to read an internal register selected
by RA0–RA3.
ACK
24
O
ACKNOWLEDGE:
Active low when NIC grants access to CPU. Used to insert
WAIT states to CPU until NIC is synchronized for a register read or write
operation.
RA0–RA3
45–48
I
REGISTER ADDRESS:
These four pins are used to select a register to be read
or written. The state of these inputs is ignored when the NIC is not in slave mode
(CS high).
PRD
44
O
PORT READ:
Enables data from external latch onto local bus during a memory
write cycle to local memory (remote write operation). This allows asynchronous
transfer of data from the system memory to local memory.
WACK
43
I
WRITE ACKNOWLEDGE:
Issued from system to NIC to indicate that data has
been written to the external latch. The NIC will begin a write cycle to place the
data in local memory.
INT
42
O
INTERRUPT:
Indicates that the NIC requires CPU attention after reception
transmission or completion of DMA transfers. The interrupt is cleared by writing
to the ISR. All interrupts are maskable.
RESET
41
I
RESET:
Reset is active low and places the NIC in a reset mode immediately, no
packets are transmitted or received by the NIC until STA bit is set. Affects
Command Register, Interrupt Mask Register, Data Configuration Register and
Transmit Configuration Register. The NIC will execute reset within 10 BUSK
cycles.
BREQ
31
O
BUS REQUEST:
Bus Request is an active high signal used to request the bus for
DMA transfers. This signal is automatically generated when the FIFO needs
servicing.
BACK
30
I
BUS ACKNOWLEDGE:
Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the NIC. If immediate bus access is desired,
BREQ should be tied to BACK.
Tying BACK to V
CC
will result in a deadlock.
PRQ, ADS1
29
O,Z
PORT REQUEST/ADDRESS STROBE 1
#
32-BIT MODE: If LAS is set in the Data Configuration Register, this line is
programmed as ADS1. It is used to strobe addresses A16–A31 into external
latches. (A16–A31 are the fixed addresses stored in RSAR0, RSAR1.) ADS1
will remain at TRI-STATE until BACK is received.
#
16-BIT MODE: If LAS is not set in the Data Configuration Register, this line is
programmed as PRQ and is used for Remote DMA Transfers. In this mode
PRQ will be a standard logic output.
NOTE: This line will power up as TRI-STATE until the Data Configuration
Register is programmed.
READY
28
I
READY:
This pin is set high to insert wait states during a DMA transfer. The NIC
will sample this signal at t3 during DMA transfers.
5
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