- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32490D (National Semiconductor Corporation) NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) PDF資料下載
參數(shù)資料
| 型號： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 52/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁
15.0 Switching Characteristics
(Continued)
Serial TimingDReceive (Beginning of Frame)
TL/F/8582–88
Symbol
Parameter
Min
Max
Units
rch
Receive Clock High Time
40
ns
rcl
Receive Clock Low Time
40
ns
rcyc
Receive Clock Cycle Time
80
120
ns
rds
Receive Data Setup Time to
Receive Clock High (Note 1)
20
ns
rdh
Receive Data Hold Time from
Receive Clock High
17
ns
pts
First Preamble Bit to Synch
(Note 2)
8
rcyc
cycles
Note 1:
All bits entering NIC must be properly decoded, if the PLL is still locking, the clock to the NIC should be disabled or CRS delayed. Any two sequential 1 data
bits will be interpreted as Synch.
Note 2:
This is a minimum requirement which allows reception of a packet.
Serial TimingDReceive (End of Frame)
TL/F/8582–89
Symbol
Parameter
Min
Max
Units
rxrck
Minimum Number of Receive Clocks
after CRS Low (Note 1)
5
rcyc
cycles
tdrb
Maximum of Allowed Dribble Bits/Clocks
(Note 2)
3
rcyc
cycles
tifg
Receive Recovery Time
(Notes 4,5)
40
rcyc
cycles
tcrsl
Receive Clock to Carrier Sense Low
(Note 3)
0
1
rcyc
cycles
Note 1:
The NIC requires a minimum number of receive clocks following the de-assertion of carrier sense (CRS). These additional clocks are provided by the
DP8391 SNI. If other decoder/PLLs are being used additional clocks should be provided. Short clocks or glitches are not allowed.
Note 2:
Up to 5 bits of dribble bits can be tolerated without resulting in a receive error.
Note 3:
Guarantees to only load bit N, additional bits up to tdrb can be tolerated.
Note 4:
This is the time required for the receive state machine to complete end of receive processing. This parameter is not measured but is guaranteed by design.
This is not a measured parameter but is a design requirement.
Note 5:
CRS must remain de-asserted for a minimum of 2 RXC cycles to be recognized as end of carrier.
52
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32828 | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| NS32829 | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| NS32FX16-15 | FILM/M CAPACITANCE=0.001 VOLT=630 |
| NS32FX16-20 | Imaging/Signal Processor |
| NS32FX16-25 | Imaging/Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32491 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Serial Network Interface |
| NS32491A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32492B | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Coaxial Transceiver Interface |
| NS32532-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32532-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。