參數(shù)資料
型號(hào)： NS32490D
廠商： National Semiconductor Corporation
英文描述： NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器)
中文描述： NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器）
文件頁(yè)數(shù)： 37/56頁(yè)
文件大?。?/td> 689K
代理商： NS32490D
13.0 Bus Arbitration and Timing
(Continued)
SLAVE MODE TIMING
When CS is low, the NIC becomes a bus slave. The CPU
can then read or write any internal registers. All register
access is byte wide. The timing for register access is shown
below. The host CPU accesses internal registers with four
address
lines,
RA0–RA3,
SRD
and
SWR
strobes.
ADS0 is used to latch the address when interfacing to a
multiplexed, address data bus. Since the NIC may be a local
bus master when the host CPU attempts to read or write to
the controller, an ACK line is used to hold off the CPU until
the NIC leaves master mode. Some number of BSCK cycles
is also required to allow the NIC to synchronize to the read
or write cycle.
Write to Register
TL/F/8582–74
Read from Register
TL/F/8582–75
TIME BETWEEN CHIP SELECTS
The NIC requires that successive chip selects be no closer
than 4 bus clocks (BSCK) together, below. If the condition is
violated, the NIC may glitch/ACK. CPUs that operate from
pipelined instructions (i.e. 386) or have a cache (i.e.
486) can execute consecutive I/O cycles very quickly. The
solution is to delay the execution of consecutive I/O cycles
by either breaking the pipeline or forcing the CPU to access
outisde it’s cache.
Time between Chip Selects
TL/F/8582–A1
37
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