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參數(shù)資料
| 型號(hào)： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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10.0 Internal Registers
(Continued)
10.3 Register Descriptions
COMMAND REGISTER (CR)
00H (READ/WRITE)
The Command Register is used to initiate transmissions, enable or disable Remote DMA operations and to select register
pages. To issue a command the microprocessor sets the corresponding bit(s) (RD2, RD1, RD0, TXP). Further commands may
be overlapped, but with the following rules: (1) If a transmit command overlaps with a remote DMA operation, bits RD0, RD1,
and RD2 must be maintained for the remote DMA command when setting the TXP bit. Note, if a remote DMA command is re-is-
sued when giving the transmit command, the DMA will complete immediately if the remote byte count register have not been re-
initialized. (2) If a remote DMA operation overlaps a transmission, RD0, RD1, and RD2 may be written with the desired values
and a ‘‘0’’ written to the TXP bit. Writing a ‘‘0’’ to this bit has no effect. (3) A remote write DMA may not overlap remote read
operation or visa versa. Either of these operations must either complete or be aborted before the other operation may start.
Bits PS1, PS0, RD2, and STP may be set any time.
7
6
5
4
3
2
1
0
PS1
PS0
RD2
RD1
RD0
TXP
STA
STP
Bit
Symbol
Description
D0
STP
STOP:
Software reset command, takes the controller offline, no packets will be received or
transmitted. Any reception or transmission in progress will continue to completion before
entering the reset state. To exit this state, the STP bit must be reset and the STA bit must be
set high. To perform a software reset, this bit should be set high. The software reset has
executed only when indicated by the RST bit in the ISR being set to a 1.
STP powers up
high.
Note:
If the NIC has previously been in start mode and the STP is set, both the STP and STA bits will remain set.
D1
STA
START:
This bit is used to activate the NIC after either power up, or when the NIC has been
placed in a reset mode by software command or error.
STA powers up low.
D2
TXP
TRANSMIT PACKET:
This bit must be set to initiate transmission of a packet. TXP is
internally reset either after the transmission is completed or aborted. This bit should be set
only after the Transmit Byte Count and Transmit Page Start registers have been
programmed.
Note:
Before the transmit command is given, the STA bit must be set and the STP bit reset.
D3, D4, D5
RD0, RD1, RD2
REMOTE DMA COMMAND:
These three encoded bits control operation of the Remote DMA
channel. RD2 can be set to abort any Remote DMA command in progress. The Remote Byte
Count Registers should be cleared when a Remote DMA has been aborted. The Remote
Start Addresses are not restored to the starting address if the Remote DMA is aborted.
RD2
RD1
RD0
0
0
0
Not Allowed
0
0
1
Remote Read
0
1
0
Remote Write (Note 2)
0
1
1
Send Packet
1
X
X
Abort/Complete Remote DMA (Note 1)
Note 1:
If a remote DMA operation is aborted and the remote byte count has not decremented to zero, PRQ (pin 29,
DIP) will remain high. A read acknowledge (RACK) on a write acknowledge (WACK) will reset PRQ low.
Note 2:
For proper operation of the Remote Write DMA, there are two steps which must be performed before using
the Remote Write DMA. The steps are as follows:
i) Write a non-zero value into RBCR0.
ii) Set bits RD2, RD1, RD0 to 0, 0, 1.
iii) Set RBCR0, 1 and RSAR0, 1
iv) Issue the Remote Write DMA Command (RD2, RD1, RD0
e
0, 1, 0)
D6, D7
PS0, PS1
PAGE SELECT:
These two encoded bits select which register page is to be accessed with
addresses RA0–3.
PS1
PS0
0
0
Register Page 0
0
1
Register Page 1
1
0
Register Page 2
1
1
Reserved
19
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