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參數(shù)資料
| 型號(hào)： | NS32490D |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NIC Network Interface Controller(NIC網(wǎng)絡(luò)接口控制器) |
| 中文描述： | NIC網(wǎng)絡(luò)接口控制器（NIC網(wǎng)絡(luò)接口控制器） |
| 文件頁(yè)數(shù)： | 39/56頁(yè) |
| 文件大?。?/td> | 689K |
| 代理商： | NS32490D |
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15.0 Switching Characteristics
AC Specs DP8390D
Note:
All Timing is Preliminary
Register Read (Latched Using ADS0)
TL/F/8582–76
Symbol
Parameter
Min
Max
Units
rss
Register Select Setup to ADS0 Low
10
ns
rsh
Register Select Hold from ADS0 Low
13
ns
aswi
Address Strobe Width In
15
ns
ackdv
Acknowledge Low to Data Valid
55
ns
rdz
Read Strobe to Data TRI-STATE
15
70
ns
rackl
Read Strobe to ACK Low (Notes 1, 3)
n
*
bcyc
a
30
ns
rackh
Read Strobe to ACK High
30
ns
rsrsl
Register Select to Slave Read Low,
Latched RS0–3 (Note 2)
10
ns
Note 1:
ACK is not generated until CS and SRD are low and the NIC has synchronized to the register access. The NIC will insert an integral number of Bus Clock
cycles until it is synchronized. In Dual Bus systems additional cycles will be used for a local or remote DMA to complete. Wait states must be issued to the CPU until
ACK is asserted low.
Note 2:
CS may be asserted before or after SRD. If CS is asserted after SRD, rackl is referenced from falling edge of CS. CS can be de-asserted concurrently with
SRD or after SRD is de-asserted.
Note 3:
These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.
39
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