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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 95/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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System Design Considerations
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
5-6
Freescale Semiconductor
5.7
Power Supply Requirements
The recommended board for the MC92604 has a minimum of two solid planes of 1-ounce copper. One
plane is to be used as a ground plane and the second plane is to be used for the 1.8-V supply. It is
recommended that the board has its own 1.8- and 3.3-V regulators with less than 50-mV ripple.
5.8
Phase-Locked Loop (PLL) Power Supply Filtering
An analog power supply is required. The PLLAVDD signal provides power for the analog portions of the
PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit
similar to the one shown in Figure 5-1. For maximum effectiveness, the filter circuit is placed as close as
possible to the PLLAVDD ball to ensure that it filters out as much noise as possible. The ground connection
should be near the PLLAGND ball. The 0.01-
F capacitor is closest to the ball, followed by the 1-F
capacitor, and finally the 1-
resistor to VDD on the 1.8-V power plane. The capacitors are connected from
PLLAGND to the ground plane. Ceramic chip capacitors with the highest possible self-resonant frequency
should be used. All traces should be kept short, wide, and direct.
Figure 5-1. PLL Power Supply Filter Circuits
TST_0, TST_1
Test mode identifiers
Must be low and remain low during normal
operation. Device must be reset if changed.
LBOE
Loopback output enable
Enable/disable transmit links during testing
(LBOE = high). No recovery action necessary,
STNDBY
Puts PLL in standby mode
Receiver must re-establish byte and word
synchronization
RESET
System reset bar
Device is reset
ENABLE_RED
Enable redundant mode
Device must be reset
Table 5-3. Asynchronous Configuration and Control Signals (continued)
Signal Name
Description
Effect of Changed State
VDD
1
0.01 F
PLLAVDD
1.0 F
GND
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