參數(shù)資料
型號： MC92604ZT
廠商： Freescale Semiconductor
文件頁數(shù)： 61/122頁
文件大小： 0K
描述： IC TXRX ETH DUAL GIG 196-MAPBGA
標準包裝： 630
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 2/2
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應商設備封裝： 196-MAPBGA（15x15）
包裝： 托盤
Receiver
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-9
If in the GMII or RGMII mode, alignment is acquired per the PCS state diagram as shown in Figure 36-9
of the IEEE Std. 802.3 2002 specification [4].
Alignment remains locked until any one of three events occur that indicate loss of alignment:
Alignment is lost when a misaligned COMMA sequence is detected. The MC92604 can be
configured to automatically realign to a new COMMA sequence. This mode is always enabled
when in backplane byte mode or GMII mode (TBIE low) or when both XMIT_x_K and TBIE are
high. If automatic realignment is allowed then alignment is lost (and immediately regained) when
a misaligned COMMA sequence is detected. A misaligned COMMA sequence is defined as four
COMMA code groups with a new alignment other than the current alignment. Non-COMMA code
groups can be dispersed between the four misaligned COMMAs; however, a properly-aligned
COMMA code group or a COMMA code group with yet another alignment breaks the sequence.
When alignment is lost due to misaligned COMMAs, the receiver is automatically aligned to the
new COMMA sequence and data continues without interruption. Also, if realignment is allowed
by the state of XMIT_x_K when in TBI mode, the FIFOs are automatically realigned to keep all
IDLE code group output relative to RECV_x_RCLK_B (see Section 3.7.1.2, “TBI Operation”). If
word synchronization is enabled, any byte realignment will cause loss of word synchronization
If the 8B/10B encoder is enabled (TBIE = low), alignment is also lost when the number of received
code groups with 8B/10B coding errors outnumbers the non-errored code groups by four. Credit
for non-errored code groups in excess of errored code groups is limited to four, such that alignment
is lost after four consecutive errored code groups. The receiver restarts its alignment procedure and
halts data flow until alignment is achieved.
Finally, the user may force loss of alignment by asserting XCVR_x_DISABLE (high). Each
receiver may thus be forced to restart its alignment procedure. Data flow will halt until alignment
is achieved. Normally, XCVR_x_DISABLE will also disable the transmitter. If this is not desired,
raising DROP_SYNC concurrent with (or prior to) XCVR_x_DISABLE will force the receiver to
re-align and have no effect on the corresponding transmitter.
NOTE
Since XCVR_x_DISABLE and DROP_SYNC are not synchronous to the
internal clock domain DROP_SYNC should be raised prior to
XCVR_x_DISABLE is raised and remain high until after
XCVR_x_DISABLE is negated low.
When establishing byte alignment, or when data flow is halted due to misalignment, the ‘Not Byte Sync’
error is reported as described in Section 3.7.3, “Error Handling.”
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