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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 92/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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System Design Considerations
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
5-3
5.4
Receiver Interface Clock Centering
All interface output drivers are internally source terminated with 50
. Therefore, no external source
terminations are required.
The receiver interface also has the option of having the output data source-aligned or source-centered with
the respective channel RECV_x_CLK. If source-aligned, then the considerations for pcb design must
include lengthening the clock trace to meet interface setup time requirements. However, the suggested
method would be to use the source-centered option to maximize the setup and hold times, keeping the
clock and data traces the same length. This applies for all modes of operation (backplane or Ethernet
compatibility and normal or reduced interface modes). For more information, see Section 3.6, “Receiver
5.5
Repeater Mode
The MC92604 may be configured into a two-link receive-transmit repeater by setting the repeater mode
enable, REPE, signal high. In repeater mode, data received on link A’s receiver is forwarded to link A’s
transmitter and link B’s receiver to link B’s transmitter. The configuration inputs may be used to control
how the repeater handles the data as it passes through the repeater. Certain configurations are more
effective than others for various applications. The transmitter at the source, the receiver at the destination,
and the repeater must have compatible configurations to ensure proper operation. The following sections
describe how each configuration control affects the repeater operation.
NOTE
The primary purpose of this mode is to facilitate bit error rate testing with
the test data driven into GEt through the receiver serial links and then is sent
back to the BERT tester through the transmitter serial links.
This mode does not attempt to meet the standard for Ethernet repeaters as
defined in Clause 41 of IEEE Std. 802.3-2002 [4].
5.5.1
Ten-Bit Interface Mode
When the device is in 10-bit interface mode (TBIE = high), the internal 8B/10B encoder and decoder are
bypassed and the 10-bit data received is forwarded directly to the transmitter. Running disparity is assumed
correct and is not checked.
When byte interface mode is enabled (TBIE = low), received data is passed through the 8B/10B decoder
where it is converted into its 8-bit data or a control byte. Running disparity and code validity are checked
and reported with the received byte at the receiver interface, as described in Section 3.8.1, “Byte Mode
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