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參數(shù)資料
| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 64/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Receiver
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-12
Freescale Semiconductor
In order to track a transmitter frequency that is offset from the receiver’s reference clock frequency, the
duty cycle and period of the RECV_x_RCLK is modulated. For example, if the transmitter is sending data
at a rate faster than the receiver, then a shortened cycle is generated as needed to track the incoming data
rate. Alternately, if the transmitter is running slower than the receiver, then a long cycle is generated. The
recovered clock duty cycle may be reduced or increased by 200 ps (if nominal frequency is 125 MHz) in
order to match the transmitter frequency. For example, if the reference clock frequency is 125 MHz, this
means that the minimum recovered clock cycle time is 7.8 ns and the maximum recovered clock cycle is
8.2 ns.
NOTE
Devices that interface to a MC92604 and are run in a recovered clock mode,
must be able to tolerate this modulated clock.
When operating in the recovered clock timing mode, the addition or deletion of IDLEs is inappropriate. If
RCCE is asserted (recovered clock timing mode), the add/delete IDLE enable, ADIE, signal must be low.
3.6.2
Reference Clock Timing Mode (RCCE = Low)
Data is timed relative to the local reference clock when RCCE is low. Synchronization between the
recovered clock and the reference clock is handled by the receiver interface. Frequency offset between the
transmitter’s reference clock and the receiver’s reference clock causes overrun/underrun situations.
Overrun occurs when the link partner’s transmitter is running faster than the receiver. Underrun occurs
when the transmitter is running slower than the receiver. To avoid overrun/underrun conditions, rate
adaption performed whereby, data is dropped or repeated to allow the data to be presented at the interface
at the local reference clock frequency. Table 3-6 summarizes the rate adaption technique as a function of
the receiver configuration when the receiver reference clock is slower than the transmitter reference clock.
Table 3-7 summarizes the rate adaption technique as a function of the receiver configuration when the
receiver reference clock is faster than the transmitter reference clock.
The ability to drop/repeat data is controlled by the ADIE configuration input. For instance, if ADIE is high
and COMPAT is low, pairs of IDLE bytes (K28.5) will be dropped/repeated. If an overrun situation is
imminent (transmitter is faster than the receiver), then the receiver interface searches for a pair of IDLE
bytes to drop. Two consecutive IDLE bytes are dropped to assure that running disparity is not affected. If
sufficient IDLE patterns are not available to drop, the receiver overrun may occur. When an overrun
occurs, the ‘overrun’ error is reported as described in Table 3-11, Table 3-14, or Table 3-15 for a 1-byte
clock period and 2 code groups of data are dropped. A sufficient number of IDLEs must be transmitted to
guard against an overrun.
The frequency of IDLEs can be computed, based on the maximum frequency offset between the
transmitter and receiver in the system. The number of bytes (code groups) that can be transmitted between
a pair of IDLEs is:
(2*106/N) – 1 bytes, where N is the frequency offset in ppm.
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