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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 103/122頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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Test Features
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
6-5
The RECV_x_ERR, RECV_x_DV, and RECV_x_COMMA signals, as interpreted and shown in
Table 6-5, have special meaning in this test mode. They report the status of the receiver and PN analysis
logic.
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode overrides the
setting on the TBIE signal and forces byte interface mode. Additionally, the BIST sequence requires that
a normal byte alignment mode be used. The setting of BSYNC is overridden, forcing the device into the
byte aligned mode, which forces BSYNC high internally.
BIST is run at the speed indicated by the frequency of the reference clock and by the speed range selected
by half-speed mode (HSE). Word sync mode is supported during BIST testing, however, only the
4-IDLEs/Non-IDLE alignment mode is supported (WSYNC1 = low and WSYNC0 = high).
The BIST sequence is as follows:
1. Enter test mode by setting the test mode inputs as described in Table 6-4.
2. If COMPAT is low, transmit 4096 IDLEs (K28.5 characters).
If COMPAT is high, an auto-negotiation sequence will occur.
3. Transmit an 8B/10B encoded PN sequence to the receiver as described above.
The transmitter will automatically go through sequences 2 and 3 on entering this test mode. When testing
is complete, the device will need to be reset before normal operation can resume.
If IDLEs are to be inserted (TST_1 = low, TST_0 = high, XCVR_A_LBE = high), then IDLEs (K28.5
code group) are inserted every 2048 code groups during sequence 3.
If COMPAT is high, /I1/I2/ code groups will be inserted instead of the IDLE (K28.5) code group.
6.3
BIST Sequence Test with Internal Digital Loopback Mode
This test mode is identical to the system BIST sequence test with external loopback mode described above,
except loopback is performed internally to GEt.
NOTE
In this mode, the configuration input LBOE controls whether serial data is
sent on transmit link outputs (XLINK_x_P and XLINK_x_N). If LBOE is
low, the link is quiescent; if LBOE is high, data is transmitted on the link).
Table 6-5. BIST Error Codes
RECV_x_ERR
RECV_x_DV
RECV_x_COMMA
Description
Low
Don’t care
Not byte/word sync. The receiver is in start-up or has lost byte
alignment and is searching for alignment.
Low
High
Low
BIST running. No PN mismatch this code group.
Low
High
BIST running. This code group is a COMMA code group.
High
Low
Don’t care
Receiver byte/word synchronized. PN analyzer is not locked.
High
Don’t care
BIST running. PN mismatch error for this code group.
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