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參數(shù)資料
| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 33/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Introduction
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
1-2
Freescale Semiconductor
1.2
Features
The MC92604 has two applications-oriented operating modes depending on the configuration. It may be
used as a backplane SerDes or an Ethernet PHY.
The main features of the MC92604 are as follows:
Common features:
— Two independent SerDes channels with full-duplex differential data links
— Configurable as a single channel device to provide redundant transmit and receive serial links
— Selectable speed range: 1.25 or 0.625 Gbaud
— Internal 8B/10B encoder/decoder that may be bypassed
— Source synchronous parallel data input interfaces
— Selectable: source-aligned or source-centered timing on the receiver output interfaces
— DDR (RGMII/RTBI), source synchronous, 4-/5-bit optional interfaces
— Parallel interfaces may be either 2.5- or 3.3-V LVTTL. Device will inter-operate with SSTL_2
with the 2.5-V LVTTL interface.
— Transmit data clock is selectable between per-channel transmit clock or channel ‘A’ transmit
clock
— Received data may be clocked to the reference clock or to the received data frequencies
— Unused transceiver channel may be disabled
— Drives 50- or 75-
media (100- or 150- differential) for lengths of up to 1.5 meters
board/backplane, or 10 meters of coax.
— Tolerates a +250 ppm frequency offset between the transmitter and receiver
— Link inputs have on-chip receiver termination and are ‘hot swap’ compatible
— Low power (less than 0.6 W) under typical conditions while operating in backplane mode with
all transceivers at full speed
— Differential LVPECL reference clock input with single-ended LVCMOS input option
— Two single-ended buffered reference clock outputs to be used as the clock source for associated
MAC interface logic.
— Built-in, at speed, self test for production testing and on-board diagnostics
— IEEE Std. 1149.1 JTAG boundary scan test support
Backplane application features:
— Link-to-link synchronization supports aligned, multi-channel word transfers. Synchronization
mechanism tolerates up to 40 bit-times of link-to-link media delay skew.
— Supports disparity-based word sync events for compatibility with legacy transceivers
— Selectable COMMA code group alignment mode enables aligned or unaligned transfers
Ethernet friendly features:
— GMII, TBI, RGMII, or RTBI data interface options
— COMMA code group alignment in receivers
— Provides the PCS and PMA layers for Ethernet PHYs as specified in IEEE Std. 802.3-2000
— MDIO slave interface and registers as defined in IEEE Std. 802.3-2002 are fully supported
— Supports rate adaption within IPG for jumbo frames up to 14 Kbytes
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